參數(shù)資料
型號(hào): M5M4V64S20ATP-8L
廠商: Mitsubishi Electric Corporation
英文描述: 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
中文描述: 64M號(hào)(4銀行甲4194304字× 4位)同步DRAM
文件頁(yè)數(shù): 29/48頁(yè)
文件大?。?/td> 1097K
代理商: M5M4V64S20ATP-8L
M5M4V64S20ATP-8, -10, -12
Jan'97
Preliminary
MITSUBISHI LSIs
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev.0.2)
29
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Output Load Condition
V
OUT
V
REF
=1.4V
50pF
50
V
TT
=1.4V
DQ
CLK
Output Timing
Measurement
Reference Point
1.4V
1.4V
1.4V
1.4V
DQ
CLK
tAC
tOH
tOHZ
Symbol Parameter
Limits
Unit
-8
-10
-12
Min.
Max.
Min.
Max.
Min.
Max.
tAC
Access time from CLK
CL=2
8
9
9.5
ns
CL=3
6
8
8
ns
tOH
Output Hold time from
CLK
CL=2
2.5
3
3
ns
CL=3
2.5
3
3
tOLZ
Delay time, output low
impedance from CLK
0
0
0
ns
tOHZ
Delay time, output high
impedance from CLK
2.5
7
3
8
3
8
ns
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