參數(shù)資料
型號(hào): M5M4V64S20ATP-8L
廠商: Mitsubishi Electric Corporation
英文描述: 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
中文描述: 64M號(hào)(4銀行甲4194304字× 4位)同步DRAM
文件頁(yè)數(shù): 23/48頁(yè)
文件大?。?/td> 1097K
代理商: M5M4V64S20ATP-8L
M5M4V64S20ATP-8, -10, -12
Jan'97
Preliminary
MITSUBISHI LSIs
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev.0.2)
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L).
Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode,
CKE is asynchronous and the only enabled input ,all other inputs including CLK are disabled and ignored,
so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable
CLK inputs, asserting DESEL or NOP command and then asserting CKE (REFSX) for longer than tSRX.
After tRC from REFSX all banks are in the idle state and a new command can be issued, but DESEL or NOP
commands must be asserted till then.
Self-Refresh
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-11
BA0,1
Self Refresh Entry
Self Refresh Exit
X
00
Stable CLK
NOP
new command
tSRX
23
minimum tRC
+1 CLOCK
for recovery
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M5M4V64S30ATP-8 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
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