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參數(shù)資料
| 型號(hào)： | M5M4V64S20ATP-10 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| 中文描述： | 64M號(hào)（4銀行甲4194304字× 4位）同步DRAM |
| 文件頁數(shù)： | 14/48頁 |
| 文件大小： | 1097K |
| 代理商： | M5M4V64S20ATP-10 |
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M5M4V64S20ATP-8, -10, -12
Jan'97
Preliminary
MITSUBISHI LSIs
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev.0.2)
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank
addresses (BA0,1). A row is indicated by the row addresses A11-0. The minimum activation interval be-
tween one bank and the other bank is tRRD.
Maximum 2 ACT commands are allowed within tRC
, although
the number of banks which are active concurrently is not limited.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the precharge
all command (PREA, PRE + A10=H) is available to deactivate them at the same time. After tRP from the
precharge, an ACT command to the same bank can be issued.
READ
After tRCD from the bank activation, a READ command can be issued. 1st output data is available after
the /CAS Latency from the READ, followed by (BL -1) consecutive data when the Burst Length is BL. The
start address is specified by A8-0 (x 8) / A9-0 (x 4), and the address sequence of burst data is defined by the
Burst Type. A READ command may be applied to any active bank, so the row precharge time (tRP) can be
hidden behind continuous output data by interleaving the multiple banks. When A10 is high at a READ
command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhibited till the internal precharge is complete. The internal precharge starts at BL after
READA. The next ACT command can be issued after (BL + tRP) from the previous READA.
Command
Bank Activation and Precharge All (BL=4, CL=3)
CLK
A0-9
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
Qa0
Qa1
Qa2
Qa3
ACT
Xb
Xb
01
PRE
tRRD
tRCD
1
ACT
Xb
Xb
01
Precharge all
tRAS
tRP
tRCmin
2 ACT command / tRCmin
A11
Xa
Xb
Xb
14
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M5M4V64S20ATP-10L | 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-12 | 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8 | 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8A | 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8L | 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M4V64S20ATP-10L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8A | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
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