參數(shù)資料
型號(hào): M59MR032C
廠商: 意法半導(dǎo)體
英文描述: 32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
中文描述: 32兆位的2Mb x16插槽,復(fù)用的I / O,雙行,突發(fā)1.8V電源快閃記憶體
文件頁(yè)數(shù): 26/49頁(yè)
文件大小: 352K
代理商: M59MR032C
M59MR032C, M59MR032D
26/49
Table 24. Burst Read Information
Table 25. Security Code Area
Offset
Data
Description
(P+F)h = 48h
0003h
Page-mode read capability
bits 0-7
’n’ such that 2
n
HEX value represents the number of read-page
bytes. See offset 28h for device word width to determine page-
mode data output width. 00h indicates no read page buffer.
(P+10)h = 49h
0003h
Number of synchronous mode read configuration fields that follow. 00h indicates no
burst capability.
(P+11)h = 4Ah
0001h
Synchronous mode read capability configuration 1
bit 3-7
bit 0-2
Reserved
’n’ such that 2
n+1
HEX value represents the maximum number of
continuous synchronous reads when the device is configured for its
maximum word width. A value of 07h indicates that the device is
capable of continuous linear bursts that will output data until the
internal burst counter reaches the end of the device’s burstable
address space. This field’s 3-bit value can be written directly to the
read configuration register bit 0-2 if the device is configured for its
maximum word width. See offset 28h for word width to determine
the burst data output width.
(P+12)h = 4Bh
0002h
Synchronous mode read capability configuration 2
(P+13)h = 4Ch
0007h
Synchronous mode read capability configuration 3
(P+14)h = 4Dh
0036h
Max operating clock frequency (MHz)
(P+15)h = 4Eh
0001h
Supported handshaking signal (WAIT pin)
bit 0
bit 1
during synchronous read
during asynchronous read
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
Offset
81h
82h
83h
84h
Data
XXXX
XXXX
XXXX
XXXX
Description
64 bits: unique device number
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