參數(shù)資料
型號(hào): M59DR008E100ZB1T
廠商: 意法半導(dǎo)體
英文描述: 8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory
中文描述: 8兆位512KB的x16插槽,雙行,第低壓閃存
文件頁數(shù): 14/37頁
文件大?。?/td> 267K
代理商: M59DR008E100ZB1T
M59DR008E, M59DR008F
14/37
Table 17. CFI Query System Interface Information
Offset
Data
Description
1Bh
0017h
V
DD
Logic Supply Minimum Program/Erase or Write voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 millivolts
1Ch
0022h
V
DD
Logic Supply Maximum Program/Erase or Write voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 millivolts
1Dh
0000h
V
PP
[Programming] Supply Minimum Program/Erase voltage
bit 7 to 4
HEX value in volts
bit 3 to 0
BCD value in 100 millivolts
Note: This value must be 0000h if no V
PP
pin is present
1Eh
00C0h
V
PP
[Programming] Supply Maximum Program/Erase voltage
bit 7 to 4
HEX value in volts
bit 3 to 0
BCD value in 100 millivolts
Note: This value must be 0000h if no V
PP
pin is present
1Fh
0004h
Typical timeout per single byte/word program (multi-byte program count = 1), 2
n
μs
(if supported; 0000h = not supported)
20h
0000h
Typical timeout for maximum-size multi-byte program or page write, 2
n
μs
(if supported; 0000h = not supported)
21h
000Ah
Typical timeout per individual block erase, 2
n
ms
(if supported; 0000h = not supported)
22h
0000h
Typical timeout for full chip erase, 2
n
ms
(if supported; 0000h = not supported)
23h
0004h
Maximum timeout for byte/word program, 2
n
times typical (offset 1Fh)
(0000h = not supported)
24h
0000h
Maximum timeout for multi-byte program or page write, 2
n
times typical (offset 20h)
(0000h = not supported)
25h
0004h
Maximum timeout per individual block erase, 2
n
times typical (offset 21h)
(0000h = not supported)
26h
0000h
Maximum timeout for chip erase, 2
n
times typical (offset 22h)
(0000h = not supported)
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