參數(shù)資料
型號: M58MR032-ZCT
廠商: 意法半導(dǎo)體
英文描述: 32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
中文描述: 32兆位的2Mb x16插槽,復(fù)用的I / O,雙行,突發(fā)1.8V電源快閃記憶體
文件頁數(shù): 1/52頁
文件大?。?/td> 396K
代理商: M58MR032-ZCT
1/52
PRELIMINARY DATA
August 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M58MR032C
M58MR032D
32 Mbit (2Mb x16, Mux I/O, Dual Bank, Burst)
1.8V Supply Flash Memory
s
SUPPLY VOLTAGE
–VDD = VDDQ = 1.7V to 2.0V for Program,
Erase and Read
–VPP = 12V for fast Program (optional)
s
MULTIPLEXED ADDRESS/DATA
s
SYNCHRONOUS / ASYNCHRONOUS READ
– Burst mode Read: 40MHz
– Page mode Read (4 Words Page)
– Random Access: 100ns
s
PROGRAMMING TIME
– 10s by Word typical
– Two or four words programming option
s
MEMORY BLOCKS
– Dual Bank Memory Array: 8/24 Mbit
– Parameter Blocks (Top or Bottom location)
s
DUAL OPERATIONS
– Read within one Bank while Program or
Erase within the other
– No delay between Read and Write operations
s
PROTECTION/SECURITY
– All Blocks protected at Power-up
– Any combination of Blocks can be protected
– 64 bit unique device identifier
– 64 bit user programmable OTP cells
– One parameter block permanently lockable
s
COMMON FLASH INTERFACE (CFI)
s
100,000 PROGRAM/ERASE CYCLES per
BLOCK
s
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M58MR032C: 88DAh
– Bottom Device Code, M58MR032D: 88DBh
FBGA
TFBGA48 (ZC)
10 x 4 ball array
Figure 1. Logic Diagram
AI90019
5
A16-A20
W
ADQ0-ADQ15
VDD
M58MR032C
M58MR032D
E
VSS
16
G
RP
WP
VDDQ VPP
L
K
WAIT
BINV
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