- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383303 > M50LPW116N (意法半導(dǎo)體) 16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory PDF資料下載
參數(shù)資料
| 型號： | M50LPW116N |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| 中文描述： | 16兆位的2Mb × 8，啟動塊3V電源低引腳數(shù)快閃記憶體 |
| 文件頁數(shù)： | 8/36頁 |
| 文件大?。?/td> | 259K |
| 代理商： | M50LPW116N |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
M50LPW116
8/36
Table 6. LPC Bus Read Field Definitions
Clock Cycle
Number
Clock
Cycle
Count
Field
LAD0-
LAD3
Memory
I/O
Description
1
1
START
0000b
I
On the rising edge of CLK with LFRAME Low, the contents
of LAD0-LAD3 must be 0000b to indicate the start of a
LPC cycle.
2
1
CYCTYPE
+ DIR
0100b
I
Indicates the type of cycle and selects 1-byte reading. Bits
3:2 must be 01b. Bit 1 indicates the direction of transfer: 0b
for read. Bit 0 is reset to 0.
3-10
8
ADDR
XXXX
I
A 32-bit address phase is transferred starting with the
most significant nibble first. A26-A31 must be set to 1. A22
= 1 for Array, A22 = 0 for registers access. For A21, A23-
A25 values, refers to Table 2.
11
1
TAR
1111b
I
The host drives LAD0-LAD3 to 1111b to indicate a
turnaround cycle.
12
1
TAR
1111b
(float)
O
The LPC Flash Memory takes control of LAD0-LAD3
during this cycle.
13-14
2
WSYNC
0101b
O
The LPC Flash Memory drives LAD0-LAD3 to 0101b
(short wait-sync) for two clock cycles, indicating that the
data is not yet available. Two wait-states are always
included.
15
1
RSYNC
0000b
O
The LPC Flash Memory drives LAD0-LAD3 to 0000b,
indicating that data will be available during the next clock
cycle.
16-17
2
DATA
XXXX
O
Data transfer is two CLK cycles, starting with the least
significant nibble.
18
1
TAR
1111b
O
The LPC Flash Memory drives LAD0-LAD3 to 1111b to
indicate a turnaround cycle.
19
1
TAR
1111b
(float)
N/A
The LPC Flash Memory floats its outputs, the host takes
control of LAD0-LAD3.
Figure 4. LPC Bus Read Waveforms
AI04429
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
START
CYCTYPE
+ DIR
ADDR
TAR
SYNC
DATA
TAR
1
1
8
2
3
2
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M50LPW116N1T | 16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW116N5T | 16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M51131L | 2 CHANNEL ELECTRONIC VOLUME BALANCE |
| M51354AP | TV IF SYSTEM |
| M51391ASP | PAL/NTSC VIDEO CHROMA DEFLECTION |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M50LPW116N1 | 功能描述:閃存 3.0V 16M (2Mx8) RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M50LPW116N1T | 制造商:Micron Technology Inc 功能描述:FLASH PARALLEL/SERL 3V/3.3V 16MBIT 2MX8 40TSOP - Tape and Reel |
| M50LPW116N5G | 功能描述:閃存 16 MBIT 3V SUPPLY RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M50LPW116N5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW116N5TG | 功能描述:閃存 16 MBIT 3V SUPPLY RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。