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參數(shù)資料
| 型號(hào)： | M50LPW116N |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| 中文描述： | 16兆位的2Mb × 8，啟動(dòng)塊3V電源低引腳數(shù)快閃記憶體 |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 259K |
| 代理商： | M50LPW116N |
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M50LPW116
10/36
The Address/Address Multiplexed (A/A Mux)
Interface
is
included
Programming equipment
programming. Only a subset of the features
available to the Low Pin Count (LPC) Interface are
available; these include all the Commands but
exclude the Security features and other registers.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux)
Interface is
selected all the blocks
unprotected. It is not possible to protect any blocks
through this interface.
Bus Read.
Bus Read operations are used to
output the contents of the Memory Array, the
Electronic Signature and the Status Register. A
valid Bus Read operation begins by latching the
Row Address and Column Address signals into
the memory using the Address Inputs, A0-A10,
and the Row/Column Address Select RC. Then
Write Enable (W) and Interface Reset (RP) must
be High, V
IH
, and Output Enable, G, Low, V
IL
, in
order to perform a Bus Read operation. The Data
Inputs/Outputs will output the value, see Figure
11, A/A Mux Interface Read AC Waveforms, and
Table 24, for details of when the output becomes
valid.
Bus Write.
Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by latching the Row Address and Column
Address signals into the memory using the
Address Inputs, A0-A10, and the Row/Column
Address Select RC. The data should be set up on
the Data Inputs/Outputs; Output Enable, G, and
Interface Reset, RP, must be High, V
IH
and Write
Enable, W, must be Low, V
IL
. The Data Inputs/
Outputs are latched on the rising edge of Write
Enable, W. See Figure 12, and Table 25, for
details of the timing requirements.
for
use
faster factory
by
Flash
for
are
Output Disable.
The data outputs are high-im-
pedance when the Output Enable, G, is at V
IH
.
Reset.
During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when RP is Low, V
IL
. RP must be
held Low, V
IL
for t
PLPH
. If RP is goes Low, V
IL
,
during a Program or Erase operation, the
operation is aborted and the memory cells affected
no longer contain valid data; the memory can take
up to t
PLRH
to abort a Program or Erase operation.
COMMAND INTERFACE
All Bus Write operations to the memory are
interpreted
by
the
Commands consist of one or more sequential Bus
Write operations.
After power-up or a Reset operation the memory
enters Read mode.
The commands are summarized in Table 11,
Commands. Refer to Table 11 in conjunction with
the text descriptions below.
Read Memory Array Command.
The Read Mem-
ory Array command returns the memory to its
Read mode where it behaves like a ROM or
EPROM. One Bus Write cycle is required to issue
the Read Memory Array command and return the
memory to Read mode. Once the command is is-
sued the memory remains in Read mode until an-
other command is issued. From Read mode Bus
Read operations will access the memory array.
While the Program/Erase Controller is executing a
Program or Erase operation the memory will not
accept the Read Memory Array command until the
operation completes.
Read Status Register Command.
The Read Sta-
tus Register command is used to read the Status
Register. One Bus Write cycle is required to issue
the Read Status Register command. Once the
Command
Interface.
Table 8. A/A Mux Bus Operations
Table 9. Manufacturer and Device Codes
Operation
G
W
RP
V
PP
DQ7-DQ0
Bus Read
V
IL
V
IH
V
IH
Don’t Care
Data Output
Bus Write
V
IH
V
IL
V
IH
V
CC
or V
PPH
Data Input
Output Disable
V
IH
V
IH
V
IH
Don’t Care
Hi-Z
Reset
V
IL
or V
IH
V
IL
or V
IH
V
IL
Don’t Care
Hi-Z
Operation
G
W
RP
A20-A1
A0
DQ7-DQ0
Manufacturer Code
V
IL
V
IH
V
IH
V
IL
V
IL
20h
Device Code
V
IL
V
IH
V
IH
V
IL
V
IH
30h
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相關(guān)代理商/技術(shù)參數(shù) |
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| M50LPW116N1 | 功能描述:閃存 3.0V 16M (2Mx8) RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M50LPW116N1T | 制造商:Micron Technology Inc 功能描述:FLASH PARALLEL/SERL 3V/3.3V 16MBIT 2MX8 40TSOP - Tape and Reel |
| M50LPW116N5G | 功能描述:閃存 16 MBIT 3V SUPPLY RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M50LPW116N5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW116N5TG | 功能描述:閃存 16 MBIT 3V SUPPLY RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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