- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377830 > M50FW080NB5TP (意法半導(dǎo)體) 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory PDF資料下載
參數(shù)資料
| 型號： | M50FW080NB5TP |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory |
| 中文描述： | 8兆1兆× 8，統(tǒng)一座3V電源閃存固件集線器 |
| 文件頁數(shù)： | 18/56頁 |
| 文件大?。?/td> | 292K |
| 代理商： | M50FW080NB5TP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
Bus operations
M50FW080
18/55
3.1.3
Bus Abort
The Bus Abort operation can be used to immediately abort the current bus operation. A Bus
Abort occurs when FWH4 is driven Low, V
IL
, during the bus operation; the memory will tri-
state the Input/Output Communication pins, FWH0-FWH3.
Note that, during a Bus Write operation, the Command Interface starts executing the
command as soon as the data is fully received; a Bus Abort during the final TAR cycles is
not guaranteed to abort the command; the bus, however, will be released immediately.
3.1.4
Standby
When FWH4 is High, V
IH
, the memory is put into Standby mode where FWH0-FWH3 are
put into a high-impedance state and the Supply Current is reduced to the Standby level,
I
CC1
.
3.1.5
Reset
During Reset mode all internal circuits are switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is in Reset mode when Interface Reset, RP,
or CPU Reset, INIT, is Low, V
IL
. RP or INIT must be held Low, V
IL
, for t
PLPH
. The memory
resets to Read mode upon return from Reset mode and the Lock Registers return to their
default states regardless of their state before Reset, see
Table 14
. If RP or INIT goes Low,
V
IL
, during a Program or Erase operation, the operation is aborted and the memory cells
affected no longer contain valid data; the memory can take up to t
PLRH
to abort a Program
or Erase operation.
3.1.6
Block Protection
Block Protection can be forced using the signals Top Block Lock, TBL, and Write Protect,
WP, regardless of the state of the Lock Registers.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M50LPW002 | 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW002K | 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW002K1T | 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW002K5T | 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW012 | 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M50G1041 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multilayer Ceramic Capacitors |
| M50G1041-F | 制造商:CDE 制造商全稱:Cornell Dubilier Electronics 功能描述:Multilayer Ceramic Capacitors COG (NPO). X7R & Z5U Capacitors |
| M50G104J1 | 功能描述:CAP CER 0.1UF 100V 5% RADIAL RoHS:否 類別:電容器 >> 陶瓷 系列:M50 標(biāo)準(zhǔn)包裝:4,000 系列:- 電容:1000pF 電壓 - 額定:50V 容差:±10% 溫度系數(shù):X7R 安裝類型:表面貼裝，MLCC 工作溫度:-55°C ~ 125°C 應(yīng)用:自動 額定值:AEC-Q200 封裝/外殼:0805（2012 公制） 尺寸/尺寸:0.079" L x 0.047" W（2.00mm x 1.20mm） 高度 - 座高（最大）:- 厚度（最大）:- 引線間隔:- 特點:- 包裝:帶卷 (TR) 引線型:- |
| M50G1241 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multilayer Ceramic Capacitors |
| M50G1241-F | 制造商:CDE 制造商全稱:Cornell Dubilier Electronics 功能描述:Multilayer Ceramic Capacitors COG (NPO). X7R & Z5U Capacitors |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。