參數(shù)資料
型號(hào)： M50FW080NB5TP
廠商： 意法半導(dǎo)體
英文描述： 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
中文描述： 8兆1兆× 8，統(tǒng)一座3V電源閃存固件集線器
文件頁(yè)數(shù)： 13/56頁(yè)
文件大?。?/td> 292K
代理商： M50FW080NB5TP
M50FW080
Signal descriptions
13/55
2.1.5
Interface configuration (IC)
The Interface Configuration input selects whether the Firmware Hub (FWH) or the
Address/Address Multiplexed (A/A Mux) Interface is used. The chosen interface must be
selected before power-up or during a Reset and, thereafter, cannot be changed. The state
of the Interface Configuration, IC, should not be changed during operation.
To select the Firmware Hub (FWH) Interface the Interface Configuration pin should be left to
float or driven Low, V
IL
; to select the Address/Address Multiplexed (A/A Mux) Interface the
pin should be driven High, V
IH
. An internal pull-down resistor is included with a value of R
IL
;
there will be a leakage current of I
LI2
through each pin when pulled to V
IH
; see
Table 20
.
2.1.6
Interface Reset (RP)
The Interface Reset (RP) input is used to reset the memory. When Interface Reset (RP) is
set Low, V
IL
, the memory is in Reset mode: the outputs are put to high impedance and the
current consumption is minimized. When RP is set High, V
IH
, the memory is in normal
operation. After exiting Reset mode, the memory enters Read mode.
2.1.7
CPU Reset (INIT)
The CPU Reset, INIT, pin is used to Reset the memory when the CPU is reset. It behaves
identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
2.1.8
Clock (CLK)
The Clock, CLK, input is used to clock the signals in and out of the Input/Output
Communication Pins, FWH0-FWH3. The Clock conforms to the PCI specification.
2.1.9
Top Block Lock (TBL)
The Top Block Lock input is used to prevent the Top Block (Block 15) from being changed.
When Top Block Lock, TBL, is set Low, V
IL
, Program and Block Erase operations in the Top
Block have no effect, regardless of the state of the Lock Register. When Top Block Lock,
TBL, is set High, V
IH
, the protection of the Block is determined by the Lock Register. The
state of Top Block Lock, TBL, does not affect the protection of the Main Blocks (Blocks 0 to
14).
Top Block Lock, TBL, must be set prior to a Program or Block Erase operation is initiated
and must not be changed until the operation completes or unpredictable results may occur.
Care should be taken to avoid unpredictable behavior by changing TBL during Program or
Erase Suspend.
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