參數(shù)資料
型號(hào): M50FLW040AK5TP
廠商: 意法半導(dǎo)體
英文描述: 4-Mbit (5 】 64 Kbyte blocks + 3 】 16 】 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory
中文描述: 4兆位(5】64字節(jié)塊3】16】4 Kbyte的)3 - V電源供電固件集線器/低引腳數(shù)的閃存
文件頁(yè)數(shù): 44/64頁(yè)
文件大?。?/td> 338K
代理商: M50FLW040AK5TP
DC and AC parameters
M50FLW040A, M50FLW040B
44/64
Figure 14.
FWH/LPC interface AC signal timing waveforms
FWH/LPC interface AC signal timing characteristics
CLK
FWH0-FWH3/
LAD0-LAD3
VALID
tCHQV
tCHQZ
tCHQX
tCHDX
tDVCH
VALID
OUTPUT DATA
FLOAT OUTPUT DATA
VALID INPUT DATA
AI09700
tCHFH
tFLCH
FWH4
START CYCLE
Table 26.
Symbol
PCI Symbol
Parameter
Value
Unit
t
CHQV
t
val
CLK to Data Out
Min
2
ns
Max
11
ns
t
CHQX(1)
t
on
CLK to Active
(Float to Active Delay)
Min
2
ns
t
CHQZ
t
off
CLK to Inactive
(Active to Float Delay)
Max
28
ns
t
AVCH
t
DVCH
t
su
Input Set-up Time
(2)
Min
7
ns
t
CHAX
t
CHDX
t
h
Input Hold Time
(2)
Min
0
ns
t
FLCH
Input Set-up time on FWH4
Min
10
ns
t
CHFH
Input Hold time on FWH4
Min
5
ns
1.
The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage
current specification.
2.
Applies to all inputs except CLK and FWH4.
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