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參數(shù)資料
| 型號： | M50FLW040AK5TP |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4-Mbit (5 】 64 Kbyte blocks + 3 】 16 】 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory |
| 中文描述： | 4兆位（5】64字節(jié)塊3】16】4 Kbyte的）3 - V電源供電固件集線器/低引腳數(shù)的閃存 |
| 文件頁數(shù)： | 25/64頁 |
| 文件大?。?/td> | 338K |
| 代理商： | M50FLW040AK5TP |
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M50FLW040A, M50FLW040B
Bus operations
25/64
Table 9.
Figure 9.
LPC bus write waveforms (1 byte)
Table 10.
LPC bus write field definitions (1 byte)
Clock
Cycle
Number
Clock
Cycle
Count
Field
LAD0-
LAD3
Memory
I/O
Description
1
1
START
0000b
I
On the rising edge of CLK with LFRAME Low,
the contents of LAD0-LAD3 must be 0000b to
indicate the start of a LPC cycle.
2
1
CYCTYPE
+ DIR
011Xb
I
Indicates the type of cycle. Bits 3:2 must be 01b.
Bit 1 indicates the direction of transfer: 1b for
write. Bit 0 is don’t care (X).
3-10
8
ADDR
XXXX
I
A 32-bit address is transferred, with the most
significant nibble first. A23-A31 must be set to 1.
A22=1 for memory access, and A22=0 for
register access.
Table 5
shows the appropriate
values for A21-A19.
11-12
2
DATA
XXXX
I
Data transfer is two cycles, starting with the
least significant nibble.
13
1
TAR
1111b
I
The host drives LAD0-LAD3 to 1111b to indicate
a turnaround cycle.
14
1
TAR
1111b
(float)
O
The LPC Flash Memory takes control of LAD0-
LAD3 during this cycle.
15
1
SYNC
0000b
O
The LPC Flash Memory drives LAD0-LAD3 to
0000b, indicating it has received data or a
command.
16
1
TAR
1111b
O
The LPC Flash Memory drives LAD0-LAD3 to
1111b, indicating a turnaround cycle.
17
1
TAR
1111b
(float)
N/A
The LPC Flash Memory floats its outputs and
the host takes control of LAD0-LAD3.
A/A Mux bus operations
Operation
G
W
RP
V
PP
DQ7-DQ0
Bus Read
V
IL
V
IH
V
IH
Don't Care
Data Output
Bus Write
V
IH
V
IL
V
IH
V
CC
or V
PPH
Data Input
Output Disable
V
IH
V
IH
V
IH
Don't Care
Hi-Z
Reset
V
IL
or V
IH
V
IL
or V
IH
V
IL
Don't Care
Hi-Z
AI04430
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
START
CYCTYPE
+ DIR
ADDR
DATA
TAR
SYNC
TAR
1
1
8
2
2
1
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M50FLW040AN5G | 4-Mbit (5 】 64 Kbyte blocks + 3 】 16 】 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory |
| M50FLW080BK5P | 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080BK5TP | 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080BN5P | 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080BN5TP | 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M50FLW040AN1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW040AN1G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW040AN1P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW040AN1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW040AN1TG | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory |
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