參數(shù)資料
型號: M50FLW040AK5TP
廠商: 意法半導(dǎo)體
英文描述: 4-Mbit (5 】 64 Kbyte blocks + 3 】 16 】 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory
中文描述: 4兆位(5】64字節(jié)塊3】16】4 Kbyte的)3 - V電源供電固件集線器/低引腳數(shù)的閃存
文件頁數(shù): 43/64頁
文件大小: 338K
代理商: M50FLW040AK5TP
M50FLW040A, M50FLW040B
DC and AC parameters
43/64
Figure 13.
FWH/LPC interface clock waveform
Table 25.
I
PP
V
PP
Supply Current
(Read/Standby)
V
PP
>
V
CC
400
μ
A
I
PP1(3)
V
PP
Supply Current
(Program/Erase active)
V
PP
= V
CC
40
mA
V
PP
= 12 V ± 5%
15
mA
1.
Input leakage currents include High-Z output leakage for all bidirectional buffers with three-state outputs.
2.
ID3 pin is RFU in LPC mode.
3.
Sampled only, not 100% tested.
FWH/LPC interface clock characteristics
Symbol
Parameter
Test Condition
Value
Unit
t
CYC
CLK Cycle Time
(1)
1.
Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz
devices may be guaranteed by design rather than tested. Refer to PCI Specification.
Min
30
ns
t
HIGH
CLK High Time
Min
11
ns
t
LOW
CLK Low Time
Min
11
ns
CLK Slew Rate
peak to peak
Min
1
V/ns
Max
4
V/ns
Table 24.
DC characteristics (continued)
Symbol
Parameter
Interface
Test Condition
Min
Max
Unit
AI03403
tHIGH
tLOW
0.6 VCC
0.5 VCC
0.4 VCC
0.3 VCC
0.2 VCC
tCYC
0.4 VCC, p-to-p
(minimum)
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