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參數(shù)資料
| 型號： | M48T254V-10ZA1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | REAL TIME CLOCK, PBGA168 |
| 封裝： | 42.50 X 42.50 MM, 1.27 MM PITCH, BGA-168 |
| 文件頁數(shù)： | 4/26頁 |
| 文件大?。?/td> | 366K |
| 代理商： | M48T254V-10ZA1 |
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M48T254V
12/26
PHANTOM CLOCK OPERATION
Communication with the Phantom Clock is estab-
lished by pattern recognition of a serial bit-stream
of 64 bits which must be matched by executing 64
consecutive WRITE cycles containing the proper
data on DQ0.
All accesses which occur prior to recognition of the
64-bit pattern are directed to memory.
After recognition is established, the next 64 READ
or WRITE cycles either extract or update data in
the clock while disabling the memory.
Data transfer to and from the timekeeping function
is accomplished with a serial bit-stream under con-
trol of Chip Enable (CE), Output Enable (OE), and
WRITE Enable (WE). Initially, a READ cycle using
the CE and OE control of the clock starts the pat-
tern recognition sequence by moving the pointer to
the first bit of the 64-bit comparison register (see
Next, 64 consecutive WRITE cycles are executed
using the CE and WE control of the device. These
64 WRITE cycles are used only to gain access to
the clock. Therefore, any address to the memory
is acceptable. However, the WRITE cycles gener-
ated to gain access to the Phantom Clock are also
writing data to a location in the mated RAM. The
preferred way to manage this requirement is to set
aside just one address location in RAM as a Phan-
tom Clock scratch pad.
When the first WRITE cycle is executed, it is com-
pared to Bit 1 of the 64-bit comparison register. If
a match is found, the pointer increments to the
next location of the comparison register and
awaits the next WRITE cycle.
If a match is not found, the pointer does not ad-
vance and all subsequent WRITE cycles are ig-
nored. If a READ cycle occurs at any time during
pattern recognition, the present sequence is abort-
ed and the comparison register pointer is reset.
Pattern recognition continues for a total of 64
WRITE cycles as described above until all of the
bits in the comparison
register have been
matched. With a correct match for 64-bits, the
Phantom Clock is enabled and data transfer to or
from the timekeeping registers can proceed. The
next 64 cycles will cause the Phantom Clock to ei-
ther receive or transmit data on DQ0, depending
on the level of the OE pin or the WE pin. Cycles to
other locations outside the memory block can be
interleaved with CE cycles without interrupting the
pattern recognition sequence or data transfer se-
quence to the Phantom Clock.
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