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| 型號(hào)： | M48T254V-10ZA1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取 |
| 英文描述： | REAL TIME CLOCK, PBGA168 |
| 封裝： | 42.50 X 42.50 MM, 1.27 MM PITCH, BGA-168 |
| 文件頁(yè)數(shù)： | 25/26頁(yè) |
| 文件大?。?/td> | 366K |
| 代理商： | M48T254V-10ZA1 |
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M48T254V
8/26
OPERATION MODES
READ
A READ cycle executes whenever WRITE Enable
(WE) is high and Chip Enable (CE) is low (see Fig-
ure 7., page 9). The distinct address defined by
the 21 address inputs (A0-A20) specifies which of
the 2M bytes of data is to be accessed. Valid data
will be accessed by the eight data output drivers
within the specified Access Time (tACC) after the
last address input signal is stable, the CE and OE
access times, and their respective parameters are
satisfied. When CE tACC and OE tACC are not sat-
isfied, then data access times must be measured
from the more recent CE and OE signals, with the
limiting parameter being tCO (for CE) or tOE (for
OE) instead of address access.
WRITE
WRITE Mode occurs whenever CE and WE sig-
nals are low (after address inputs are stable, see
most recent falling edge of CE and WE will deter-
mine when the WRITE cycle begins (the earlier,
rising edge of CE or WE determines cycle termina-
tion). All address inputs must be kept stable
throughout the WRITE cycle. WE must be high (in-
active) for a minimum recovery time (tWR) before a
subsequent cycle is initiated. The OE control sig-
nal should be kept high (inactive) during the
WRITE cycles to avoid bus contention. If CE and
OE are low (active), WE will disable the outputs for
Output Data WRITE Time (tODW) from its falling
edge.
Data Retention Mode
Data can be read or written only when VCC is
greater than VPFD. When VCC is below VPFD (the
point at which write protection occurs), the clock
registers and the SRAM are blocked from any ac-
cess. When VCC falls below the Battery Switch
Over threshold (VSO), the device is switched from
VCC to battery backup (VBAT). RTC operation and
SRAM data are maintained via battery backup un-
til power is stable. All control, data, and address
signals must be powered down when VCC is pow-
ered down.
The lithium power source is designed to provide
power for RTC activity as well as RTC and RAM
data retention when VCC is absent or unstable.
The capability of this source is sufficient to power
the device continuously for the life of the equip-
ment into which it has been installed. For specifi-
cation purposes, life expectancy is ten (10) years
at 25°C with the internal oscillator running without
VCC. The actual life expectancy will be much long-
er if no battery energy is used (e.g., when VCC is
present).
Table 2. Operating Modes
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage
1. See Table 9., page 20 for details.
Mode
VCC
CE
OE
WE
DQ7-DQ0
Power
Deselect
3.0V to 3.6V
VIH
X
High-Z
Standby
WRITE
VIL
X
VIL
DIN
Active
READ
VIL
VIH
DOUT
Active
READ
VIL
VIH
High-Z
Active
Deselect
VSO to VPFD (min)
(1)
X
High-Z
CMOS Standby
Deselect
≤ VSO(1)
X
High-Z
Battery Back-Up
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