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參數(shù)資料
| 型號： | M48T254V-10ZA1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復及定時提取 |
| 英文描述： | REAL TIME CLOCK, PBGA168 |
| 封裝： | 42.50 X 42.50 MM, 1.27 MM PITCH, BGA-168 |
| 文件頁數(shù)： | 2/26頁 |
| 文件大?。?/td> | 366K |
| 代理商： | M48T254V-10ZA1 |
M48T254V
10/26
Figure 9. Memory WRITE Cycle, Chip Enable Controlled
Note: 1. OE = VIH or VIL. If OE = VIH during a WRITE cycle, the output buffers remain in a high impedance state.
2. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high
impedance state during this period.
AI05656
DQ0–DQ7
ADDRESSES
WE
CE
DATA IN
STABLE
tAH2
tOEW
tWC
tODW
tDS
tDH2
tCOE
tWP
tAW
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