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參數(shù)資料
| 型號： | M44C892 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁數(shù)： | 40/84頁 |
| 文件大小： | 643K |
| 代理商： | M44C892 |
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M44C892
M44C892
M44C092
Rev. A5, 14-Dec-01
45 (84)
Timer 3 – Mode 7: Carrier Frequency Burst Modulation Controlled by SSI Internal Output (SO)
The Timer 3 counter is driven by an internal or external clock source. Its compare– and compare mode registers must
be programmed to generate the carrier frequency via the output toggle flip-flop. The output (SO) of the SSI is used
to enable or disable the Timer 3 output. The SSI should be supplied with the toggle signal of Timer 2 (see combination
mode 12).
Timer 3 – Mode 8: FSK Modulation with Shift Register Data (SO)
The two compare registers are used for generating two different time intervals. The SSI internal data output (SO) selects
which compare register is used for the output frequency generation. A ’0’ level at the SSI data output enables the
compare register 1. An ’1’ level enables compare register 2. The both compare- and compare mode registers must be
programmed to generate the two frequencies via the output toggle flip-flop. The SSi can be supplied with the toggle
signal of Timer 2. The Timer 3 counter is driven by an internal or external clock source. The Timer 2 counter is driven
by the Counter 3 (TOG3) (see also combination mode 13).
01234012340123
Counter 3
CM31
CM32
SO
13815
401201201201201201201 20123
T3R
40
T3O
1
01
0
Figure 51. FSK modulation
Timer 3 – Mode 9: Pulse-Width Modulation with the Shift Register
The two compare registers are used for generating two different time intervals. The SSI internal data output (SO) selects
which compare register is used for the output pulse generation. In this mode both compare- and compare mode registers
must be programmed for generating the two pulse widths. It is also useful to enable the single-action mode for extreme
duty cycles. Timer 2 is used as baudrate generator and for the trigger restart of Timer 3. The SSI must be supplied with
a toggle signal of Timer 2. The counter is driven by an internal or external clock source (see combination mode 7).
0000 00000
000 0
Counter 3
CM31
CM32
T3O
13816
000001 2345 6789 1011121314150 12345
TOG2
67 8
1
91112
10
14
13
0
2 3
14
15
0
01
SIR
SO
SCO
T3R
Figure 52. Pulse-width modulation
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