參數(shù)資料
型號： M44C892
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20
封裝： SSO-20
文件頁數(shù)： 25/84頁
文件大?。?/td> 643K
代理商： M44C892
M44C892
M44C892
M44C092
Rev. A5, 14-Dec-01
31 (84)
Watchdog Control Register (WDC)
Address: ’7’hex – Subaddress: ’A’hex
Bit 3 *
Bit 2
Bit 1
Bit 0
WDC
WDL
WDR
WDT1
WDT0
Reset value: 1111b
* Bit 3 –> MSB, Bit 0 –> LSB
WDL
WatchDog Lock mode
WDL = 1, the watchdog can be enabled and disabled by using the WDR-bit
WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no effect. After the
WDL-bit is cleared, the watchdog is active until a system reset or power-on reset occurs.
WDR
WatchDog Run and stop mode
WDR = 1, the watchdog is stopped / disabled
WDR = 0, the watchdog is active / enabled
WDT1
WatchDog Time 1
WDT0
WatchDog Time 0
Both these bits control the time interval for the watchdog reset
WDT1
WDT0 Divider
Delay Time to Reset with
SUBCL = 32 kHz
Delay Time to Reset with
SYSCL = 2 / 1 MHz
0
512
15.625 ms
0.256 ms / 0.512 ms
0
1
2048
62.5 ms
1.024 ms / 2.048 ms
1
0
16384
0.5 s
8.2 ms / 16.4 ms
1
131072
4 s
65.5 ms / 131 ms
3.3.2
Timer 2
Features: 8/12 bit timer for
D Interrupt, square-wave, pulse and duty cycle
generation
D Baud-rate generation for the internal shift register
D Manchester and Biphase modulation together with the
SSI
D Carrier frequency generation and modulation
together with the SSI
Timer 2 can be used as interval timer for interrupt
generation, as signal generator or as baud-rate generator
and modulator for the serial interface. It consists of a 4-bit
and an 8-bit up counter stage which both have compare
registers. The 4-bit counter stages of Timer 2 are
cascadable as 12-bit timer or as 8-bit timer with 4-bit
prescaler. The timer can also be configured as 8-bit timer
and separate 4-bit prescaler.
The Timer 2 input can be supplied via the system clock,
the external input clock (T2I), the Timer 1 output clock,
the Timer 3 output clock or the shift clock of the serial
interface. The external input clock T2I is not synchro-
nized with SYSCL. Therefore it is possible to use Timer 2
with a higher clock speed than SYSCL. Furthermore with
that input clock the Timer 2 operates in the power-down
mode SLEEP (CPU core –> sleep and OSC–Stop –> yes)
as well as in the POWER-DOWN (CPU core –> sleep and
OSC–Stop –> no). All other clock sources supplied no
clock signal in SLEEP. The 4-bit counter stages of Timer
2 have an additional clock output (POUT).
Its output has a modulator stage that allows the generation
of pulses as well as the generation and modulation of
carrier frequencies. The Timer 2 output can modulate
with the shift register data output to generate Biphase- or
Manchester-code.
If the serial interface is used to modulate a bitstream, the
4-bit stage of Timer 2 has a special task. The shift register
can only handle bitstream lengths divisible by 8. For other
lengths, the 4-bit counter stage can be used to stop the
modulator after the right bitcount is shifted out.
If the timer is used for carrier frequency modulation, the
4-bit stage works together with an additional 2-bit duty
cycle generator like a 6-bit prescaler to generate carrier
frequency and duty cycle. The 8-bit counter is used to en-
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