參數(shù)資料
型號： M44C892
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20
封裝： SSO-20
文件頁數(shù)： 32/84頁
文件大?。?/td> 643K
代理商： M44C892
M44C892
M44C092
Rev. A5, 14-Dec-01
38 (84)
Timer 2 Mode Register 1 (T2M1)
Address: ’7’hex – Subaddress: ’1’hex
Bit 3
Bit 2
Bit 1
Bit 0
T2M1
T2D1
T2D0
T2MS1
T2MS0
Reset value: 1111b
T2D1
Timer 2 Duty cycle bit 1
T2D0
Timer 2 Duty cycle bit 0
T2D1
T2D0
Function of Duty Cycle Generator (DCG)
Additional Divider Effect
1
1
Bypassed (DCGO0)
/ 1
1
0
Duty cycle 1/1 (DCGO1)
/ 2
0
1
Duty cycle 1/2 (DCGO2)
/ 3
0
0
Duty cycle 1/3 (DCGO3)
/ 4
T2MS1
Timer 2 Mode Select bit 1
T2MS0
Timer 2 Mode Select bit 0
Mode
T2MS1
T2MS0
Clock Output (POUT)
Timer 2 Modes
1
1
1
4-bit counter overflow (OVF1)
12-bit compare counter; the DCG
has to be bypassed in this mode
2
1
0
4-bit compare output (CM1)
8-bit compare counter with 4-bit
programmable prescaler and duty
cycle generator
3
0
1
4-bit compare output (CM1)
8-bit compare counter clocked by
SYSCL or the external clock input
T2I, 4-bit prescaler run, the
counter 2/1 starts after writing
mode 3
4
0
0
4-bit compare output (CM1)
8-bit compare counter clocked by
SYSCL or the external clock input
T2I, 4-bit prescaler stop and resets
Duty Cycle Generator
The duty cycle generator generates duty cycles from 25%, 33% or 50%. The frequency at the duty cycle generator
output depends on the duty cycle and the Timer 2 prescaler setting. The DCG-stage can also be used as additional
programmable prescaler for Timer 2.
DCGIN
DCGO0
DCGO1
DCGO2
DCGO3
13807
Figure 43. DCG output signals
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