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參數(shù)資料
| 型號： | M44C892 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁數(shù)： | 24/84頁 |
| 文件大小： | 643K |
| 代理商： | M44C892 |
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M44C892
M44C092
Rev. A5, 14-Dec-01
30 (84)
Timer 1 Control Register 1 (T1C1)
Address: ’7’hex – Subaddress: ’8’hex
Bit 3 *
Bit 2
Bit 1
Bit 0
T1C1
T1RM
T1C2
T1C1
T1C0
Reset value: 1111b
* Bit 3 –> MSB, Bit 0 –> LSB
T1RM
Timer 1 Restart Mode
T1RM = 0, write access without Timer 1 restart
T1RM = 1, write access with Timer 1 restart
Note: if WDL = 0, Timer 1 restart is impossible
T1C2
Timer 1 Control bit 2
T1C1
Timer 1 Control bit 1
T1C0
Timer 1 Control bit 0
The three bits T1C[2:0] select the divider for timer 1. The
resulting time interval depends on this divider and the
timer 1 input clock source. The timer input can be sup-
plied by the system clock, the 32kHz oscillator or via the
clock management. If the clock management generates
the SUBCL, the selected input clock from the RC oscilla-
tor, 4MHz oscillator or an external clock is divided by 16.
T1C2
T1C1
T1C0
Divider
Time Interval with SUBCL
Time Interval with
SUBCL = 32 kHz
Time Interval with
SYSCL = 2/1 MHz
0
2
SUBCL / 2
61
s
1
s / 2 s
0
1
4
SUBCL / 4
122
s
2
s / 4 s
0
1
0
8
SUBCL / 8
244
s
4
s / 8 s
0
1
16
SUBCL / 16
488
s
8
s / 16 s
1
0
32
SUBCL / 32
0.977 ms
16
s / 32 s
1
0
1
256
SUBCL / 256
7.812 ms
128
s / 256 s
1
0
2048
SUBCL / 2048
62.5 ms
1024
s / 2048 s
1
16384
SUBCL / 16384
500 ms
8192
s / 16384 s
Timer 1 Control Register 2 (T1C2)
Address: ’7’hex – Subaddress: ’9’hex
Bit 3 *
Bit 2
Bit 1
Bit 0
T1C2
– – –
T1BP
T1CS
T1IM
Reset value: x111b
* Bit 3 –> MSB, Bit 0 –> LSB
T1BP
Timer 1 SUBCL ByPassed
T1BP = 1, TIOUT = T1MUX
T1BP = 0, T1OUT = SUBCL
T1CS
Timer 1 input Clock Select
T1CS = 1, CL1 = SUBCL (see figure 28)
T1CS = 0, CL1 = SYSCL (see figure 28)
T1IM
Timer 1 Interrupt Mask
T1IM = 1, disables Timer 1 interrupt
T1IM = 0, enables Timer 1 interrupt
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