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參數(shù)資料
| 型號： | M440T513Y-15ZA9 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | REAL TIME CLOCK, PBGA168 |
| 封裝： | PLASTIC, BGA-168 |
| 文件頁數(shù)： | 6/26頁 |
| 文件大小： | 453K |
| 代理商： | M440T513Y-15ZA9 |
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M440T513Y
14/26
CLOCK OPERATION
Clock Registers
Registers 00h, 01h, 02h, 04h, 06h, 08h, 09h, and
0Ah contain the time of day data in BCD. Eleven
bits within these eight registers are not used and
will always read '0' regardless of how they are writ-
ten. Bits 6 and 7 in the Months Register (09h) are
binary bits. When set to logic '0,' EOSC (Bit 7) en-
ables the Real Time Clock oscillator. This bit will
normally be turned on by the user during device
initialization. However, the oscillator can be turned
on and off as necessary by setting this bit to the
appropriate level. Bit 6 of the Hours Register is de-
fined as the 12- or 24-hour select bit. When set to
logic '1,' the 12-hour format is selected. In the 12-
hour format, Bit 5 is the AM/PM bit with logic '1' be-
ing PM. In the 24-hour mode, Bit 5 is the second
10-hour bit (20-23 hours). The Clock Registers are
updated every 0.01 seconds from the Real Time
Clock, except when the TE Bit (Bit 7 of Register
0Bh) is set low or the clock oscillator is not running.
Reading and Setting the Clock
The preferred method of synchronizing data ac-
cess to and from the TIMEKEEPER is to access
the Command Register by doing a WRITE cycle to
address location 0Bh and setting TE Bit (Transfer
Enable Bit) to a logic '0.' This will freeze the Exter-
nal Clock Registers at the present recorded time,
allowing access to occur without danger of simul-
taneous update. When the clock registers have
been read or written, a second WRITE cycle to lo-
cation 0Bh and setting the TE Bit to a logic '1' will
put the Clock Registers back to being updated ev-
ery 0.01 second. No time is lost in the Real Time
Clock because the internal copy of the Clock Reg-
ister buffers is continually incremented while the
external memory registers are frozen. An alternate
method of reading and writing the Clock Registers
is to ignore synchronization. However, any single
READ may give erroneous data as the Real Time
Clock may be in the process of updating the exter-
nal memory registers as data is being read. The in-
ternal copies of seconds through years are
incremented, and the time of day alarm is checked
during the period that hundreds of seconds reads
“99” to “00.” A way of making sure data is valid is
to do multiple READs and compare. Writing the
registers can also produce erroneous results for
the same reasons. A way of making sure that the
WRITE cycle has caused proper update is to do a
READ to verify and re-execute the WRITE cycle if
data is not correct. While the possibility of errone-
ous results from READ and WRITE cycles has
been stated, it is worth noting that the probability
of an incorrect result is kept to a minimum due to
the redundant structure of the TIMEKEEPER.
Clock Alarm Registers
Registers 03h, 05h, and 07h contain the Clock
Alarm Registers. Bits 3, 4, 5, and 6 of Register 07h
will always read '0' regardless of how they are writ-
ten. Bit 7 of Registers 03h, 05h, and 07h are mask
bits (see Table 6., page 15). When all of the mask
bits are logic '0,' a Clock Alarm will only occur
when Registers 02h, 04h, and 06h match the val-
ues stored in Registers 03h, 05h, and 07h. An
alarm will be generated every day when Bit 7 of
Register 07h is set to a logic '1.' Similarly, an alarm
is generated every hour when Bit 7 of Registers
07h and 05h is set to a logic '1.' When Bit 7 of Reg-
isters 07h, 05h, and 03h is set to a logic '1,' an
alarm will occur every minute when Register 1
(seconds) rolls from “59” to “00.”
Clock Alarm Registers are written and read in the
same format as the Clock Registers. The Clock
Alarm Flag and Interrupt are always cleared when
alarm Registers are read or written.
Watchdog Alarm Registers
Registers 0Ch and 0Dh contain the time for the
watchdog alarm. The two registers contain a time
count from 00.01 to 99.99 seconds in BCD. The
value written into the Watchdog Alarm Registers
can be written or read in any order. Any access to
Register 0Ch or 0Dh will cause the watchdog
alarm to re-initialize and clears the Watchdog Flag
Bit and the Watchdog Interrupt Output. When a
new value is entered or the Watchdog Registers
are read, the watchdog timer will start counting
down from the entered value to zero. When zero is
reached, the Watchdog Interrupt Output will go to
the active state. The watchdog timer countdown is
interrupted and re-initialized back to the entered
value every time either of the registers are access-
ed. In this manner, controlled periodic accesses to
the watchdog timer can prevent the watchdog
alarm from going to an active level. If access does
not occur, the countdown alarm will be repetitive.
The Watchdog Alarm Registers always read the
entered value. The actual countdown register is in-
ternal and is not readable. Writing registers 0Ch
and 0Dh to '0' will disable the watchdog alarm fea-
ture.
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