參數(shù)資料
型號(hào)： M440T513Y-15ZA9
廠商： STMICROELECTRONICS
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： REAL TIME CLOCK, PBGA168
封裝： PLASTIC, BGA-168
文件頁數(shù)： 25/26頁
文件大?。?/td> 453K
代理商： M440T513Y-15ZA9
M440T513Y
8/26
OPERATION MODES
Memory READ Mode
The M440T513Y is in the 32-bit READ Mode
whenever W1 - W4 (WRITE Enable Byte 1 to 4)
are high and E1 - E4 – Chip Enable Bytes 1 to 4
are low (see Table 2., page 8). The unique ad-
dress specified by the 19 address inputs defines
which one of the 524,288 long words of data is to
be accessed. Valid data will be available at the
Data I/O pins within Address Access Time (tAVQV)
after the last address input signal is stable, provid-
ing the E1-4 and G access times are also satisfied.
If the E1-4 and G access times are not met, valid
data will be available after the latter of the Chip En-
able Access Times (tELQV) or Output Enable Ac-
cess Time (tGLQV).
The state of the thirty-two three-state Data I/O sig-
nals is controlled by E1-4 and G. If the outputs are
activated before tAVQV, the data lines will be driven
to an indeterminate state until tAVQV. If the Ad-
dress Inputs are changed while E1-4 and G re-
main active, output data will remain valid for
Output Data Hold Time (tAXQX) but will go indeter-
minate until the next Address Access.
Clock READ Mode
The clock is in the READ Mode whenever WC
(Clock WRITE Enable) is high and EC (Clock Chip
Enable) is low. The unique address specified by
the 6 Address Inputs defines which one of the 64
bytes of clock data is to be accessed. Valid data
will be available at the Data I/O pins (DQC0-7)
within Address Access Time (tAVQV) after the last
address input signal is stable, providing the EC
and GC access times are also satisfied. If the EC
and GC access times are not met, valid data will
be available after the latter of the Chip Enable Ac-
cess Times (tELQV) or Output Enable Access Time
(tGLQV).
The state of the eight three-state Data I/O signals
is controlled by EC and G. If the outputs are acti-
vated before tAVQV, the data lines will be driven to
an indeterminate state until tAVQV. If the Address
Inputs are changed while EC and G remain active,
output data will remain valid for Output Data Hold
Time (tAXQX) but will go indeterminate until the
next Address Access. See section on Reading and
Setting the Clock under CLOCK OPERATION for
more details.
Table 2. Memory Operating Modes
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
1. See Table 12., page 20 for details.
Mode
VCC
E4
E3
E2
E1
G
W4
W3
W2
W1
DQ24-
DQ31
DQ16-
DQ23
DQ8-
DQ15
DQ0-
DQ7
Power
Byte WRITE
4.5 to 5.5V
H
L
H
X
L
Hi-Z
DIN
Active
Byte WRITE
H
L
H
X
L
X
Hi-Z
DIN
Hi-Z
Active
Byte WRITE
H
L
H
X
L
X
Hi-Z
DIN
Hi-Z
Active
Byte WRITE
L
HH
L
X
DIN
Hi-Z
Active
Byte WRITE
X
L
H
L
Hi-Z
DIN
Active
Byte WRITE
X
L
X
H
L
H
Hi-Z
DIN
Hi-Z
Active
Byte WRITE
X
L
X
H
L
H
Hi-Z
DIN
Hi-Z
Active
Byte WRITE
L
X
H
L
H
DIN
Hi-Z
Active
Long Word
WRITE
LL
H
L
DIN
Active
Byte READ
H
L
X
H
Hi-Z
DOUT
Active
Byte READ
H
L
H
L
X
H
X
Hi-Z
DOUT
Hi-Z
Active
Byte READ
H
L
H
L
X
H
X
Hi-Z
DOUT
Hi-Z
Active
Byte READ
L
H
L
H
X
DOUT
Hi-Z
Active
Long Word
READ
LL
L
H
DOUT DOUT DOUT DOUT
Active
Deselect
H
X
Hi-Z
Stdby
Deselect
VSO to
VPFD(min)
(1)
X
Hi-Z
CMOS
Standby
Deselect
≤ VSO(1)
X
Hi-Z
Battery
Back-up
Mode
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