參數(shù)資料
型號: M41T56MH6F
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: REAL TIME CLOCK, PDSO28
封裝: 0.330 INCH, SNAPHAT, LEAD FREE, PLASTIC, SOH-28
文件頁數(shù): 5/28頁
文件大?。?/td> 244K
代理商: M41T56MH6F
M41T56
Operation
2.3
WRITE mode
In this mode the master transmitter transmits to the M41T56 slave receiver. Bus protocol is
shown in Figure 11 on page 13. Following the START condition and slave address, a logic '0'
(R/W = 0) is placed on the bus and indicates to the addressed device that word address An
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
memory location within the RAM on the reception of an acknowledge clock. The M41T56
slave receiver will send an acknowledge clock to the master transmitter after it has received
the slave address and again after it has received the word address and each data byte (see
2.4
Data retention mode
With valid VCC applied, the M41T56 can be accessed as described above with READ or
WRITE cycles. Should the supply voltage decay, the M41T56 will automatically deselect,
write protecting itself when VCC falls between VPFD (max) and VPFD (min). This is
accomplished by internally inhibiting access to the clock registers and SRAM.
When VCC
falls below the Battery Back-up Switchover Voltage (VSO), power input is switched from the
VCC pin to the battery and the clock registers and SRAM are maintained from the attached
battery supply.
All outputs become high impedance. On power up, when VCC returns to a nominal value,
write protection continues for tREC.
For a further more detailed review of battery lifetime calculations, please see Application
Note AN1012.
Figure 11.
WRITE mode sequence
AI00591
BUS ACTIVITY:
ACK
S
ACK
STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n
DATA n+1
DATA n+X
WORD
ADDRESS (n)
SLAVE
ADDRESS
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