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參數(shù)資料
| 型號： | M41T56MH6F |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | REAL TIME CLOCK, PDSO28 |
| 封裝： | 0.330 INCH, SNAPHAT, LEAD FREE, PLASTIC, SOH-28 |
| 文件頁數(shù)： | 28/28頁 |
| 文件大?。?/td> | 244K |
| 代理商： | M41T56MH6F |
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M41T56
Operation
2.1.3
Stop data transfer
A change in the state of the data line, from Low to High, while the clock is High, defines the
STOP condition.
2.1.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the High period of the clock signal. The data on the line may be
changed during the Low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition, a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
2.1.5
Acknowledge
Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low
level put on the bus by the receiver, whereas the master generates an extra acknowledge
related clock pulse.
A slave receiver which is addressed is obliged to generate an acknowledge after the
reception of each byte. Also, a master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable Low during the High period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case, the transmitter must leave the data line High to enable the master to generate the
STOP condition.
Figure 5.
Serial bus data transfer sequence
AI00587
DATA
CLOCK
DATA LINE
STABLE
DATA VALID
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M41T60Q6F | 1 TIMER(S), REAL TIME CLOCK, QCC16 |
| M44C510-P40 | 4-BIT, MROM, MICROCONTROLLER, PDIP40 |
| M44C510D-XXX-DOW | 4-BIT, MROM, MICROCONTROLLER |
| M44C588 | 4-BIT, MROM, 4 MHz, MICROCONTROLLER |
| M44C892 | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M41T56MH6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 bit (64 bit x8) Serial Access TIMEKEEPER SRAM |
| M41T56SH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 bit 64b x8 Serial Access TIMEKEEPER SRAM |
| M41T60 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial Access Real-Time Clock |
| M41T60_05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial access real-time clock |
| M41T60_10 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial access real-time clock |
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