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參數(shù)資料
| 型號： | M41T56MH6F |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | REAL TIME CLOCK, PDSO28 |
| 封裝： | 0.330 INCH, SNAPHAT, LEAD FREE, PLASTIC, SOH-28 |
| 文件頁數(shù)： | 27/28頁 |
| 文件大?。?/td> | 244K |
| 代理商： | M41T56MH6F |
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Operation
M41T56
2
Operation
The M41T56 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 64 bytes
contained in the device can then be accessed sequentially in the following order:
1.
Seconds register
2.
Minutes register
3.
Century/hours register
4.
Day register
5.
Date register
6.
Month register
7.
Years register
8.
Control register
9.
RAM
The clock continually monitors VCC for an out of tolerance condition. Should VCC fall below
VPFD, the device terminates an access in progress and resets the device address counter.
Inputs to the device will not be recognized at this time to prevent erroneous data from being
written to the device from an out of tolerance system. When VCC falls below VBAT, the device
automatically switches over to the battery and powers down into an ultra low current mode
of operation to conserve battery life. Upon power-up, the device switches from battery to
VCC at VBAT and recognizes inputs when VCC goes above VPFD volts.
2.1
2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one
bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the
SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
Data transfer may be initiated only when the bus is not busy.
●
During data transfer, the data line must remain stable whenever the clock line is High.
●
Changes in the data line while the clock line is High will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain High.
2.1.2
Start data transfer
A change in the state of the data line, from High to Low, while the clock is High, defines the
START condition.
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| M41T60Q6F | 1 TIMER(S), REAL TIME CLOCK, QCC16 |
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| M44C510D-XXX-DOW | 4-BIT, MROM, MICROCONTROLLER |
| M44C588 | 4-BIT, MROM, 4 MHz, MICROCONTROLLER |
| M44C892 | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M41T56MH6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 bit (64 bit x8) Serial Access TIMEKEEPER SRAM |
| M41T56SH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 bit 64b x8 Serial Access TIMEKEEPER SRAM |
| M41T60 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial Access Real-Time Clock |
| M41T60_05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial access real-time clock |
| M41T60_10 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial access real-time clock |
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