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參數(shù)資料
| 型號： | M41T56MH6F |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復及定時提取 |
| 英文描述： | REAL TIME CLOCK, PDSO28 |
| 封裝： | 0.330 INCH, SNAPHAT, LEAD FREE, PLASTIC, SOH-28 |
| 文件頁數(shù)： | 3/28頁 |
| 文件大?。?/td> | 244K |
| 代理商： | M41T56MH6F |
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M41T56
Operation
2.2
READ mode
In this mode, the master reads the M41T56 slave after setting the slave address (see
Figure 8 on page 12 and Figure 9 on page 12). Following the WRITE Mode Control Bit (R/W
= 0) and the Acknowledge Bit, the word address An is written to the on-chip address pointer.
Next the START condition and slave address are repeated, followed by the READ Mode
Control Bit (R/W = 1). At this point, the master transmitter becomes the master receiver. The
data byte which was addressed will be transmitted and the master receiver will send an
Acknowledge Bit to the slave transmitter. The address pointer is only incremented on
reception of an Acknowledge Bit. The M41T56 slave transmitter will now place the data byte
at address An + 1 on the bus. The master receiver reads and acknowledges the new byte
and the address pointer is incremented to An + 2. This cycle of reading consecutive
addresses will continue until the master receiver sends a STOP condition to the slave
transmitter.
An alternate READ mode may also be implemented, whereby the master reads the M41T56
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer, see Figure 10 on page 12.
Table 2.
AC characteristics
Symbol
Parameter(1)
1.
Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V (except where noted).
Min
Max
Unit
fSCL
SCL clock frequency
0
100
kHz
tLOW
Clock low period
4.7
s
tHIGH
Clock high period
4
s
tR
SDA and SCL rise time
1
s
tF
SDA and SCL fall time
300
ns
tHD:STA
START condition hold time
(after this period the first clock pulse is generated)
4s
tSU:STA
START condition setup time
(only relevant for a repeated start condition)
4.7
s
tSU:DAT
Data setup time
250
ns
tHD:DAT
(2)
2.
Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling
edge of SCL.
Data hold time
0
s
tSU:STO
STOP condition setup time
4.7
s
tBUF
Time the bus must be free before a new transmission
can start
4.7
s
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|---|---|
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M41T56MH6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 bit (64 bit x8) Serial Access TIMEKEEPER SRAM |
| M41T56SH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 bit 64b x8 Serial Access TIMEKEEPER SRAM |
| M41T60 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial Access Real-Time Clock |
| M41T60_05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial access real-time clock |
| M41T60_10 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial access real-time clock |
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