參數(shù)資料
型號: M41T256YMH7TR
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復及定時提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO44
封裝: 0.330 INCH, PLASTIC, SOH-44
文件頁數(shù): 8/30頁
文件大?。?/td> 271K
代理商: M41T256YMH7TR
Operating modes
M41T256Y
VCC. This can significantly extend the lifetime of the battery, when non-volatile operation is
not needed.
Note:
The Sleep Mode will remove power from the RAM array only and not affect the data
retention of the TIMEKEEPER Registers (7FF0h through 7FFFh - this includes the
Calibration Register).
The Sleep Mode (SLP) Bit located in register 7FF8h (D6), must be set to a '1' by the user
while the device is powered by VCC. This will “arm” the Sleep Mode latch, but not actually
disconnect the RAM array from power until the next power-down cycle. This protects the
user from immediate data loss in the event he inadvertently sets the SLP Bit. Once VCC falls
below VSO (VBAT), the Sleep Mode circuit will be engaged and the RAM array will be
isolated from the battery, resulting in both a lower battery current, and a loss of RAM data.
Note:
Upon initial battery attach or initial power application without the battery, the state of the
SLP Bit will be undetermined. Therefore, the SLP Bit should be initialized to '0' by the user.
Additional current reduction can be achieved by setting the STOP (ST) Bit in register 7FF9h
(D7), turning off the clock oscillator. This combination will result in the longest possible
battery life, but also loss of time and data. When the device is again powered-up, the user
should first read the SLP Bit to determine if the device is currently in Sleep Mode, then reset
the bit to '0' in order to disable the Sleep Mode (this will NOT be automatically taken care of
during the power-up).
Note:
See AN1570, “M41T256Y Sleep Mode Function” for more information on Sleep Mode and
battery lifetimes.
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