參數(shù)資料
型號: M41T00
廠商: 意法半導體
英文描述: Serial Access TIMEKEEPER
中文描述: 串行訪問計時
文件頁數(shù): 6/15頁
文件大?。?/td> 99K
代理商: M41T00
M41T00
6/15
Table 9. Power Down/Up AC Characteristics
(1)
(T
A
= –40 to 85°C)
Symbol
Note: 1. V
CC
fall time should not exceed 5mV/μs.
Parameter
Min
Max
Unit
t
PD
SCL and SDA at V
IH
before Power Down
0
ns
t
REC
SCL and SDA at V
IH
after Power Up
10
μs
Acknowledge.
Each byte of eight bits is followed
by one acknowledge bit. This acknowledge bit is a
low level put on the bus by the receiver, whereas
the master generates an extra acknowledge relat-
ed clock pulse.
A slave receiver which is addressed is obliged to
generate an acknowledge after the reception of
each byte. Also, a master receiver must generate
an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case, the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
Figure 5. Power Down/Up Mode AC Waveforms
AI00596
VCC
tREC
tPD
VSO
SDA
SCL
DON'T CARE
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