參數(shù)資料
型號: M41ST87WMX6T
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO28
封裝: 0.300 INCH, PLASTIC, SOIC-28
文件頁數(shù): 9/38頁
文件大小: 552K
代理商: M41ST87WMX6T
17/38
M41ST87Y, M41ST87W
Figure 16. Tamper Detect Output Options
Figure 17. Basic Tamper Detect Options
Tamper Detect Sampling (TDS1 and TDS2).
This bit selects between a 1Hz sampling rate or
constant monitoring of the Tamper Input Pin(s) to
detect a tamper event when the Normally Closed
switch mode is selected. This allows the user to re-
duce the current drain when the TEBX Bit is en-
abled while the device is in battery backup (see
Table 8). Sampling is disabled if the TCMX Bit is
set to logic '1' (Normally Open). In this case the
state of the TDSX Bit is a “Don’t care.”
Note: The crystal oscillator must be “On” for sam-
pling to be enabled.
Tamper Current Hi/Tamper Current Lo (TCHI/
TCLO1 and TCHI/TCLO2). This bit selects the
strength of the internal pull-up or pull-down used
during the sampling of the Normally Closed condi-
AI07821
IRQ - Interrupt the
processor on tamper
User
Configuration
TPCLR - Clear external
RAM on tamper
RESET OUT
CLR - Clear 128 bytes
internal RAM on tamper
Time tag tamper
event (to RTC)
CLR1EXT
TIE1
CLR1
CLR2EXT
TIE2
CLR2
(other reset sources)
TEB2
TP2
TEB1
TP1
AI07818
TAMPER LO,
NORMALLY OPEN
TAMPER HI,
NORMALLY CLOSED
User
Configuration
(TCM
X, TPMX)
IRQ - Interrupt the
processor on tamper
TPCLR - Clear external
RAM on tamper
CLR - Clear internal
RAM on tamper
Time tag tamper
event
CLRX
EXT
TIE
X
CLRX
TAMPER HI,
NORMALLY OPEN
TAMPER LO,
NORMALLY CLOSED
Triggering Event
Tamper Event Output
TCMX, TPMX = 1,1
TCMX, TPMX = 0,0
TCMX, TPMX = 1,0
TCMX, TPMX = 0,1
VCC (VOUT)
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