參數(shù)資料
型號: M41ST87WMX6T
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO28
封裝: 0.300 INCH, PLASTIC, SOIC-28
文件頁數(shù): 6/38頁
文件大?。?/td> 552K
代理商: M41ST87WMX6T
M41ST87Y, M41ST87W
14/38
Figure 13. Alternate READ Mode Sequence
WRITE Mode
In this mode the master transmitter transmits to
the M41ST87Y/W slave receiver. Bus protocol is
shown in Figure 14, page 14. Following the
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the ad-
dressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST87Y/W slave receiver will send
an acknowledge clock to the master transmitter af-
ter it has received the slave address (see Figure
11, page 13) and again after it has received the
word address and each data byte.
Figure 14. WRITE Mode Sequence
AI00895
BUS ACTIVITY:
ACK
S
ACK
NO
ACK
STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n
DATA n+1
DATA n+X
SLAVE
ADDRESS
AI00591
BUS ACTIVITY:
ACK
S
ACK
STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n
DATA n+1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
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