參數(shù)資料
型號: M41ST87WMX6T
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO28
封裝: 0.300 INCH, PLASTIC, SOIC-28
文件頁數(shù): 24/38頁
文件大?。?/td> 552K
代理商: M41ST87WMX6T
M41ST87Y, M41ST87W
30/38
Power-on Reset
The M41ST87Y/W continuously monitors VCC.
When VCC falls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for tREC after VCC passes VPFD(max).
The RST pin is an open drain output and an appro-
priate pull-up resistor should be chosen to control
rise time.
Note: A Power-on Reset will result in resetting the
following control bits to '0': OFIE, AFE, ABE,
SQWE, FT, WDS, BMB0-BMB4, RB0, RB1, TIE1,
and TIE2 (see Table 17, page 33).
Reset Inputs (RSTIN1 & RSTIN2)
The M41ST87Y/W provides two independent in-
puts which can generate an output reset. The
function of these resets is identical to a reset gen-
erated by a power cycle. Table 14 and Figure 25
illustrate the AC reset characteristics of this func-
tion. Pulses shorter than tR1 and tR2 will not gener-
ate a reset condition. RSTIN1 and RSTIN2 are
each internally pulled up to VCC through a 100k
resistor.
Figure 25. RSTIN1 & RSTIN2 Timing Waveforms
Table 14. Reset AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
2. Pulse widths of less than 100ns will result in no RESET (for noise immunity).
3. Programmable (see Table 16, page 32). Same function as Power-on Reset.
Symbol
Parameter(1)
Min
Max
Unit
tR1
(2)
RSTIN1 Low to RST Low (min pulse width)
100
200
ns
tR2
(2)
RSTIN2 Low to RSTIN2 High (min pulse width)
100
200
ns
tREC
(3)
RSTIN1 or RSTIN2 High to RST High
96
98(3)
ms
AI07072
RSTIN1
RST
RSTIN2
tR1
tREC
Hi-Z
tR2
tREC
Hi-Z
相關(guān)PDF資料
PDF描述
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