參數(shù)資料
型號: M40Z111WSH
廠商: 意法半導(dǎo)體
英文描述: NVRAM CONTROLLER for up to TWO LPSRAM
中文描述: NVRAM中控制器長達(dá)2 LPSRAM
文件頁數(shù): 7/12頁
文件大?。?/td> 89K
代理商: M40Z111WSH
Symbol
Parameter
Min
Max
Unit
t
F (1)
V
PFD
(max) to V
PFD
(min) V
CC
Fall Time
300
μ
s
t
FB (2)
V
PFD
(min) to V
SO
V
CC
Fall Time
10
μ
s
t
R
V
PFD
(min) to V
PFD
(max) V
CC
Rise Time
10
μ
s
t
EDL
Chip Enable Propagation Delay
M40Z111
15
ns
M40Z111W
20
ns
t
EDH
Chip Enable Propagation Delay
M40Z111
10
ns
M40Z111W
20
ns
t
ER
Chip Enable Recovery
40
200
ms
t
WP
Write Protect Time
M40Z111
40
150
μ
s
M40Z111W
40
250
μ
s
Notes
: 1. V
PFD
(max) to V
PFD
(min) fall time of less than t
F
may result in deselection/write protection not occurring until 200
μ
s after
V
CC
passes V
PFD
(min).
2. V
PFD
(min) to V
SO
fall time of less than t
FB
may cause corruption of RAM data.
Table 6. Power Down/Up AC Characteristics
(T
A
= 0 to 70
°
C)
AI02396
VCC
VPFD (max)
E
ECON
tF
tFB
VOHB
VPFD (min)
VSO
tWPT
VPFD
Figure 5. Power Down Timing
7/12
M40Z111, M40Z111W
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