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參數(shù)資料
| 型號(hào)： | M40Z111WSH |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | NVRAM CONTROLLER for up to TWO LPSRAM |
| 中文描述： | NVRAM中控制器長(zhǎng)達(dá)2 LPSRAM |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 89K |
| 代理商： | M40Z111WSH |
AI02239B
8
9
10
11
12
13
14
2
3
4
5
6
7
22
21
20
19
18
17
16
15
28
27
26
25
24
23
1
NC
NC
NC
NC
THS
VSS
NC
NC
NC
VCC
NC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
E
NC
ECON
NC
NC
VOUT
VCC
M40Z111
M40Z111W
Figure 2. SOIC Pin Connections
Warning:
NC = Not Connected.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
°
C
T
STG
Storage Temperature (V
CC
Off)
SNAPHAT
SOIC
–40 to 85
–55 to 125
°
C
T
SLD (2)
Lead Solder Temperature for 10 seconds
260
°
C
V
IO
Input or Output Voltages
–0.3 to V
CC
+0.3
V
V
CC
Supply Voltage
–0.3 to 7
V
I
O
Output Current
20
mA
P
D
Power Dissipation
1
W
Notes:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260
°
C for 10 seconds (total thermal budget not to exceed 150
°
C for longer than 30 seconds).
CAUTION:
Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
CAUTION:
Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 2. Absolute Maximum Ratings
(1)
When an invalid V
CC
condition occurs, the condi-
tioned chip enable (E
CON
) output is forced inactive
to write-protect the stored data in the SRAM.
During a power failure, the SRAM is switched from
the V
CC
pin to the lithium cell within the SNAPHAT
to provide the energy required for data retention.
On a subsequent power-up, the SRAM remains
write protected until a valid power condition returns.
The 28 pin 330mil SOIC provides sockets with gold
plated contacts at both ends for direct connection
to a separate SNAPHAT housing containing the
battery. The unique design allows the SNAPHAT
battery package to be mounted on top of the SOIC
package after the completion of the surface mount
process. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to the
high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion. The SOIC and battery
packages are shipped separately in plastic anti-
static tubes or in Tape & Reel form. For the 28 lead
SOIC, the battery package (i.e. SNAPHAT) part
number is "M4Z28-BR00SH1" or "M4Z32-
BR00SH1" (See Table 7).
OPERATION
The M40Z111/111W, as shown in Figure 4, can
control up to two standard low-power SRAMs.
These SRAMs must be configured to have the chip
enable input disable all other input signals. Most
slow, low-power SRAMs are configured like this,
however many fast SRAMs are not. During normal
operating conditions, the conditioned chip enable
(E
CON
) output pin follows the chip enable (E) input
pin with timing shown in Table 6. An internal switch
connects V
CC
to V
OUT
. This switch has a voltage
drop of less than 0.3V (I
OUT1
).
DESCRIPTION
(cont’d)
2/12
M40Z111, M40Z111W
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