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參數(shù)資料
| 型號： | M40Z111WSH |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | NVRAM CONTROLLER for up to TWO LPSRAM |
| 中文描述： | NVRAM中控制器長達2 LPSRAM |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 89K |
| 代理商： | M40Z111WSH |
When V
CC
degrades during a power failure,E
CON
is forced inactive independent of E. In this situation,
the SRAM is unconditionally write protected as V
CC
falls below an out-of-tolerance threshold (V
PFD
).
The power fail detection value associated with V
PFD
is selected by the THS pin and is shown in Table 5.
(Note: THS pin must be connected to either V
SS
or
V
OUT
). If chip enable access is in progress during
a power fail detection, that memory cycle continues
to completion before the memory is write protected.
If the memory cycle is not terminated within time
t
WP
, E
CON
is unconditionally driven high, write pro-
tecting the SRAM.
A power failure during a write cycle may corrupt
data at the currently addressed location, but does
not jeopardize the rest of the SRAM’s contents. At
voltages below V
PFD
(min), the user can be assured
the memory will be write protected provided the
V
CC
fall time exceeds t
F
.
As V
CC
continues to degrade, the internal switch
disconnects V
CC
and connects the internal battery
to V
OUT
. This occurs at the switchover voltage
(V
SO
). Below the V
SO
, the battery provides a volt-
age V
OHB
to the SRAM and can supply current
I
OUT2
(see Table 5). When V
CC
rises above V
SO
,
V
OUT
is switched back to the supply voltage. Output
E
CON
is held inactive for t
ER
(200ms maximum)
after the power supply has reached V
PFD
, inde-
pendent of the E input, to allow for processor
stabilization (see Figure 6).
DATA RETENTION LIFETIME CALCULATION
Most low power SRAMs on the market today can
be used with the M40Z111/111W NVRAM Control-
ler. There are, however some criteria which should
be used in making the final choice of which SRAM
to use. The SRAM must be designed in a way
where the chip enable input disables all other in-
puts to the SRAM. This allows inputs to the
M40Z111/111W and SRAMs to be Don’t Care once
V
CC
falls below V
PFD
(min). The SRAM should also
guarantee data retention down to V
CC
=2.0V. The
chip enable access time must be sufficient to meet
the system needs with the chip enable propagation
delays included. If the SRAM includes a second
chip enable pin (E2), this pin should be tied to V
OUT
.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular SRAMs
being evaluated. Most SRAMs specify a data re-
tention current at 3.0V.
AI02394
VCC
E
ECON
VSS
VOUT
VCC
CMOS
SRAM
x8 or x16
3.3V or 5V
THS
E
0.1
μ
F
0.1
μ
F
M40Z111
Thereshold
1N5817 or
MBR5120T3
Figure 3. Hardware Hookup
3/12
M40Z111, M40Z111W
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M40Z111MH | Multiconductor Cable; Number of Conductors:8; No. Strands x Strand Size:Solid; Jacket Material:Polyvinylchloride (PVC); Number of Pairs:4; Leaded Process Compatible:Yes |
| M40Z300 | NVRAM CONTROLLER for up to EIGHT LPSRAM |
| M40Z300MH | NVRAM CONTROLLER for up to EIGHT LPSRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M40Z300 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V or 3V NVRAM supervisor for up to 8 LPSRAMs |
| M40Z300_05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V or 3V NVRAM Supervisor for Up to 8 LPSRAMs |
| M40Z300_07 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V or 3V NVRAM supervisor for up to 8 LPSRAMs |
| M40Z300_10 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5 V or 3 V NVRAM supervisor for up to 8 LPSRAMs |
| M40Z300AV | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3V NVRAM Supervisor for Up to 8 LPSRAMs |
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