- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383298 > M390S6453ET1-C7A (SAMSUNG SEMICONDUCTOR CO. LTD.) 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor PDF資料下載
參數(shù)資料
| 型號： | M390S6453ET1-C7A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | 168線注冊模塊，基于256Mb電子芯片的72位ECC |
| 文件頁數(shù)： | 17/26頁 |
| 文件大小： | 662K |
| 代理商： | M390S6453ET1-C7A |
256MB, 512MB, 1GB Registered DIMM
Rev. 1.4 May 2004
SDRAM
3.3V
1200
870
Output
50pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Vtt = 1.4V
50
Output
50pF
Z0 = 50
(Fig. 2) AC output load circuit
(Fig. 1) DC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V, T
A
= 0 to 70
°
C)
Parameter
Value
Unit
AC input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
Notes :
Parameter
Symbol
Version
Unit
Note
7A
Row active to row active delay
t
RRD
(min)
15
ns
1
RAS to CAS delay
t
RCD
(min)
20
ns
1
Row precharge time
t
RP
(min)
20
ns
1
Row active time
t
RAS
(min)
45
ns
1
t
RAS
(max)
100
us
Row cycle time
t
RC
(min)
65
ns
1
Last data in to row precharge
t
RDL
(min)
2
CLK
2,5
Last data in to Active delay
t
DAL
(min)
2 CLK + tRP
-
5
Last data in to new col. address delay
t
CDL
(min)
1
CLK
2
Last data in to burst stop
t
BDL
(min)
1
CLK
2
Col. address to col. address delay
t
CCD
(min)
1
CLK
3
Number of valid output data
CAS latency=3
2
ea
4
CAS latency=2
1
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP
相關PDF資料 |
PDF描述 |
|---|---|
| M392T5160CJA-CF7 | DDR2 Registered SDRAM MODULE |
| M393T1G60CJA-CE6 | DDR2 Registered SDRAM MODULE |
| M393T5160CZ3-CD5 | DDR2 Registered SDRAM MODULE |
| M393T5160CZA-CF7 | DDR2 Registered SDRAM MODULE |
| M393T5660CZ3-CD5 | DDR2 Registered SDRAM MODULE |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M3-91 | 制造商:Southco 功能描述: |
| M3910 BK001 | 制造商:Alpha Wire Company 功能描述:CBL 9COND 10AWG BLK 1000' |
| M3910 BK002 | 制造商:Alpha Wire Company 功能描述:CBL 9COND 10AWG BLK 500' |
| M3910 BK005 | 制造商:Alpha Wire Company 功能描述:CBL 9COND 10AWG BLK 100' |
| M3910 BK199 | 制造商:Alpha Wire Company 功能描述:CBL 9COND 10AWG BLK 3000=3000' |
發(fā)布緊急采購，3分鐘左右您將得到回復。