參數(shù)資料
型號: M390S6453ET1-C7A
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor
中文描述: 168線注冊模塊,基于256Mb電子芯片的72位ECC
文件頁數(shù): 13/26頁
文件大?。?/td> 662K
代理商: M390S6453ET1-C7A
256MB, 512MB, 1GB Registered DIMM
Rev. 1.4 May 2004
SDRAM
td, tr = Delay of register
Notes :
1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register. Therefore, Input/Output signals of read/write function should be
issued 1CLK earlier as compared to Unbuffered DIMMs.
2. D
IN
is to be issued 1clock after write command in external timing because D
IN
is issued directly to module.
: Don
t
care
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
REG
Control Signal(RAS,CAS,WE)
*1
*2
*3
D
OUT
*1. Register Input
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLK
RAS
CAS
WE
RAS
CAS
WE
tSAC
tRDL
Read
Command
Row Active
Row Active
Write
Command
Precharge
Command
1CLK
td
tr
td
tr
*2. Register Output
*3. SDRAM
tRAC(refer to *1)
CAS latency(refer to *1)
=2CLK+1CLK
DQ
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
Precharge
Command
CAS latency(refer to *2)
=2CLK
tRAC(refer to *2)
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