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參數(shù)資料
| 型號： | M38B79MFH-XXXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 80/112頁 |
| 文件大?。?/td> | 1862K |
| 代理商： | M38B79MFH-XXXXFP |
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
4
Table 1 Pin description (1)
Pin
Name
Function
VCC, VSS
Power source
Apply voltage of 4.0–5.5 V to VCC
, and 0 V to VSS.
CNVSS
Connect to VSS.
VPP power input pin in flash memory mode.
VEE
Pull-down
Apply voltage supplied to pull-down resistors of ports P0, P1, P2 and P3.
power source
VREF
Reference voltage
Reference voltage input pin for A-D converter.
AVSS
Analog power
Analog power source input pin for A-D converter.
source
Connect to VSS.
______
RESET
Reset input
Reset input pin for active “L”.
XIN
Clock input
Input and output pins for the main clock generating circuit.
Feedback resistor is built in between XIN pin and XOUT pin.
Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the
XOUT
Clock output
oscillation frequency.
When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
The clock is used as the oscillating source of system clock.
P00/FLD8–
Output port P0
8-bit output port.
FLD automatic display
P07/FLD15
High-breakdown-voltage P-channel open-drain output structure.
pins
A pull-down resistor is built in between port P0 and the VEE pin.
At reset, this port is set to VEE level.
P10/FLD16– I/O port P1
8-bit I/O port.
FLD automatic display
P17/FLD23
I/O direction register allows each pin to be individually programmed as either pins
input or output.
At reset, this port is set to input mode.
Low-voltage input level.
High-breakdown-voltage P-channel open-drain output structure.
A pull-down resistor is built in between port P1 and the VEE pin.
At reset, this port is set to VEE level.
P20/FLD0–
Output port P2
8-bit output port with the same function as port P0.
FLD automatic display
P27/FLD7
High-breakdown-voltage P-channel open-drain output structure.
pins
A pull-down resistor is built in between port P2 and the VEE pin.
At reset, this port is set to VEE level.
P30/FLD24–
I/O port P3
8-bit I/O port with the same function as port P1.
FLD automatic display
P37/FLD31
Low-voltage input level.
pins
High-breakdown-voltage P-channel open-drain output structure.
A pull-down resistor is built in between port P3 and the VEE pin.
At reset, this port is set to VEE level.
P40/FLD32– I/O port P4
8-bit I/O port with the same function as port P1.
FLD automatic display
P47/FLD39
Low-voltage input level.
pins
High-breakdown-voltage P-channel open-drain output structure.
A pull-down resistor is not built in between port P4 and the VEE pin.
P50/FLD40– I/O port P5
8-bit I/O port with the same function as port P1.
FLD automatic display
P57/FLD47
Low-voltage input level.
pins
High-breakdown-voltage P-channel open-drain output structure.
A pull-down resistor is not built in between port P5 and the VEE pin.
P60/FLD48– I/O port P6
4-bit I/O port with the same function as port P1.
FLD automatic display
P63/FLD51
Low-voltage input level.
pins
High-breakdown-voltage P-channel open-drain output structure.
A pull-down resistor is not built in between port P6 and the VEE pin.
Function except a port function
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