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參數(shù)資料
| 型號(hào)： | M38B79MFH-XXXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 40/112頁 |
| 文件大小： | 1862K |
| 代理商： | M38B79MFH-XXXXFP |
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
30
(1) Serial I/O1 operation
Either the internal synchronous clock or external synchronous
clock can be selected by the serial I/O1 synchronous clock selec-
tion bits (b2 and b3 of address 001916) of serial I/O1 control
register 1 as synchronous clock for serial transfer.
The internal synchronous clock has a built-in dedicated divider
where 7 different clocks are selected by the internal synchronous
clock selection bits (b5, b6 and b7 of address 001C16) of serial
I/O1 control register 3.
The PB1/SRDY1, PB2/SBUSY1, and PB3/Spins each select ei-
ther I/O port or handshake I/O signal by the serial I/O1
synchronous clock selection bits (b2 and b3 of address 001916) of
serial I/O1 control register 1 as well as the PB1/SRDY1 PB2/
SBUSY1 pin control bits (b0 to b3 of address 001A16) of serial
I/O1 control register 2.
For the SOUT1 being used as an output pin, either CMOS output
or N-channel open-drain output is selected by the PB5/SOUT1 P-
channel output disable bit (b7 of address 001A16) of serial I/O1
control register 2.
Either output active or high-impedance can be selected as a
SOUT1 pin state at serial non-transfer by the SOUT1 pin control bit
(b6 of address 001A16) of serial I/O1 control register 2. However,
when the external synchronous clock is selected, perform the fol-
lowing setup to put the SOUT1 pin into a high-impedance state:
When the SCLK1 input is “H” after completion of transfer, set the
SOUT1 pin control bit to “1”.
When the SCLK1 input goes to “L” after the start of the next serial
transfer, the SOUT1 pin control bit is automatically reset to “0” and
put into an output active state.
Regardless of whether the internal synchronous clock or external
synchronous clock is selected, the full duplex mode and the trans-
mit-only mode are available for serial transfer, one of which is
selected by the transfer mode selection bit (b5 of address 001916)
of serial I/O1 control register 1.
Either LSB first or MSB first is selected for the I/O sequence of the
serial transfer bit strings by the transfer direction selection bit (b6
of address 001916) of serial I/O1 control register 1.
When using serial I/O1, first select either 8-bit serial I/O or auto-
matic transfer serial I/O by the serial transfer selection bits (b0 and
b1 of address 001916) of serial I/O1 control register 1, after
completion of the above bit setup. Next, set the serial I/O initializa-
tion bit (b4 of address 001916) of serial I/O1 control register 1 to
“1” (Serial I/O enable) .
When stopping serial transfer while data is being transferred, re-
gardless of whether the internal or external synchronous clock is
selected, reset the serial I/O initialization bit (b4) to “0”.
Fig. 23 Structure of serial I/O1 control register 3
b7 b6 b5
b4 b3
b2 b1 b0
Serial I/O1 control register 3
(SIO1CON3 (SC13): address 001C16)
Automatic transfer interval set bits
b4b3b2b1b0
0 0 0 0 0: 2 cycles of transfer clocks
0 0 0 0 1: 3 cycles of transfer clocks
:
1 1 1 1 0: 32 cycles of transfer clocks
1 1 1 1 1: 33 cycles of transfer clocks
Data is written to a latch and read from a decrement counter.
Internal synchronous clock selection bits
b7b6b5
0 0 0: f(XIN)/4 or f(XCIN)/8
0 0 1: f(XIN)/8 or f(XCIN)/16
0 1 0: f(XIN)/16 or f(XCIN)/32
0 1 1: f(XIN)/32 or f(XCIN)/64
1 0 0: f(XIN)/64 or f(XCIN)/128
1 0 1: f(XIN)/128 or f(XCIN)/256
1 1 0: f(XIN)/256 or f(XCIN)/512
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