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參數(shù)資料
| 型號： | M38867E8AFS |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 51/110頁 |
| 文件大?。?/td> | 1601K |
| 代理商： | M38867E8AFS |
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51
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
A-D CONVERTER
[A-D Conversion Register 1,2 (AD1, AD2)]
0035
16
, 0038
16
The A-D conversion register is a read-only register that stores the
result of an A-D conversion. When reading this register during an
A-D conversion, the previous conversion result is read.
Bit 7 of the A-D conversion register 2 is the conversion mode se-
lection bit. When this bit is set to “0,” the A-D converter becomes
the 10-bit A-D mode. When this bit is set to “1,” that becomes the
8-bit A-D mode. The conversion result of the 8-bit A-D mode is
stored in the A-D conversion register 1. As for 10-bit A-D mode,
10-bit reading or 8-bit reading can be performed by selecting the
reading procedure of the A-D conversion register 1, 2 after A-D
conversion is completed (in Figure 48).
The A-D conversion register 1 performs the 8-bit reading inclined
to MSB after reset, the A-D conversion is started, or reading of the
A-D converter register 1 is generated; and the register becomes
the 8-bit reading inclined to LSB after the A-D converter register 2
is generated.
[AD/DA Control Register (ADCON)] 0034
16
The AD/DA control register controls the A-D conversion process.
Bits 0 to 2 select a specific analog input pin. Bit 3 signals the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion, and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AV
SS
and V
REF
into 1024, and outputs the divided voltages in the
10-bit A-D mode (256 division in 8-bit A-D mode).
The A-D converter successively compares the comparison voltage
V
ref
in each mode, dividing the V
REF
(see below), with the input
voltage.
10-bit A-D mode (10-bit reading)
V
REF
1024
V
ref
=
n (n = 0–1023)
10-bit A-D mode (8-bit reading)
V
REF
256
V
ref
=
n (n = 0–255)
8-bit A-D mode
V
REF
V
ref
=
(n–0.5) (n = 1–255)
=0
(n = 0)
Fig. 47 Structure of AD/DA control register
Channel Selector
The channel selector selects one of ports P6
0
/AN
0
to P6
7
/AN
7
,
and inputs the voltage to the comparator.
Comparator and Control Circuit
The comparator and control circuit compares an analog input volt-
age with the comparison voltage, and then stores the result in the
A-D conversion registers 1, 2. When an A-D conversion is com-
pleted, the control circuit sets the A-D conversion completion bit
and the A-D interrupt request bit to “1”.
Note that because the comparator consists of a capacitor cou-
pling, set f(X
IN
) to 500 kHz or more during an A-D conversion.
256
Fig. 48 Structure of 10-bit A-D mode reading
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