參數(shù)資料
型號(hào)： M38867E8AFS
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 43/110頁(yè)
文件大?。?/td> 1601K
代理商： M38867E8AFS
43
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 38 Structure of I
2
C control register
[I
2
C Control Register (S1D)] 0015
16
The I
2
C control register (address 0015
16
) controls data communi-
cation format.
Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. The I
2
C interrupt request signal occurs immediately
after the number of count specified with these bits (ACK clock is
added to the number of count when ACK clock is selected by ACK
bit (bit 7 of address 0016
16
)) have been transferred, and BC0 to
BC2 are returned to “000
2
”.
Also when a START condition is received, these bits become
“000
2
” and the address data is always transmitted and received in
8 bits.
Bit 3: I
2
C interface enable bit (ES0)
This bit enables to use the multi-master I
2
C BUS interface. When
this bit is set to “0,” the use disable status is provided, so that the
S
DA
and the S
CL
become high-impedance. When the bit is set to
“1,” use of the interface is enabled.
When ES0 = “0,” the following is performed.
PIN = “1,” BB = “0” and AL = “0” are set (which are bits of the I
2
C
status register at address 0014
16
).
Writing data to the I
2
C data shift register (address 0012
16
) is dis
abled.
Bit 4: Data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses.
When this bit is set to “0,” the addressing format is selected, so
that address data is recognized. When a match is found between
a slave address and address data as a result of comparison or
when a general call (refer to “(5) I
2
C Status Register,” bit 1) is re-
ceived, transfer processing can be performed. When this bit is set
to “1,” the free data format is selected, so that slave addresses are
not recognized.
Bit 5: Addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit
is set to “0,” the 7-bit addressing format is selected. In this case,
only the high-order 7 bits (slave address) of the I
2
C address regis-
ter (address 0013
16
) are compared with address data. When this
bit is set to “1,” the 10-bit addressing format is selected, and all
the bits of the I
2
C address register are compared with address
data.
Bit 6: System clock stop selection bit (CLKSTP)
When executing the WIT or STP instruction, this bit selects the
condition of system clock provided to the multi-master I
2
C-BUS in-
terface. When this bit is set to “0,” system clock and operation of
the multi-master I
2
C-BUS interface stop by executing the WIT or
STP instruction.
When this bit is set to “1,” system clock and operation of the multi-
master I
2
C-BUS interface do not stop even when the WIT
instruction is executed.
When the system clock stop selection bit is “1,” do not execute the
STP instruction.
Bit 7: I
2
C-BUS interface pin input level selection bit
This bit selects the input level of the S
CL
and S
DA
pins of the multi-
master I
2
C-BUS interface.
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