參數(shù)資料
型號(hào)： M38827G5-XXXHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù)： 17/64頁(yè)
文件大?。?/td> 619K
代理商： M38827G5-XXXHP
Rev.1.01
Nov 14, 2005
page 22 of 60
REJ03B0089-0101
3882 Group
Fig. 15 Interrupt control
Fig. 16 Structure of interrupt-related registers (1)
Interrupt disable flag (I)
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
0 : No interrupt request issued
1 : Interrupt request issued
Interrupt request register 2
CNTR0/INT0 interrupt request bit
CNTR1/INT1 interrupt request bit
Not used (returns “0” when read)
INT2 interrupt request bit
INT3 interrupt request bit
INT4 interrupt request bit
key-on wake-up interrupt request bit
Not used (returns “0” when read)
(IREQ2 : address 003D16)
Interrupt control register 2
CNTR0/INT0 interrupt enable bit
CNTR1/INT1 interrupt enable bit
Not used (returns “0” when read)
INT2 interrupt enable bit
INT3 interrupt enable bit
INT4 interrupt enable bit
key-on wake-up interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
(ICON2 : address 003F16)
Interrupt edge selection register
INT0 active edge selection bit
INT1 active edge selection bit
Not used (returns “0” when read)
INT2 active edge selection bit
INT3 active edge selection bit
INT4 active edge selection bit
INT5 active edge selection bit
Not used (returns “0” when read)
(INTEDGE : address 003A16)
Interrupt request register 1
INT0/input buffer full interrupt request
bit
INT1/output buffer empty interrupt
request bit
LRESET request bit
Not used (returns “0” when read)
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2/INT5 interrupt request bit
Interrupt control register 1
INT0/input buffer full interrupt enable bit
INT1/output buffer empty interrupt enable
bit
LRESET enable bit
Not used (returns “0” when read)
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2/INT5 interrupt enable bit
(IREQ1 : address 003C16)
(ICON1 : address 003E16)
0 : Falling edge active
1 : Rising edge active
b7
b0
b7
b0
b7
b0
b7
b0
b7
b0
0
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