- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45047 > M38588GCFP 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDSO42 PDF資料下載
參數(shù)資料
| 型號(hào)： | M38588GCFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDSO42 |
| 封裝： | 8.40 X 17.50 MM, 0.80 MM PITCH, PLASTIC, SSOP-42 |
| 文件頁(yè)數(shù)： | 71/77頁(yè) |
| 文件大?。?/td> | 824K |
| 代理商： | M38588GCFP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)當(dāng)前第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)
Rev.1.10
Apr 3, 2006
page 73 of 75
REJ03B0139-0110
3858 Group
2. Notes when selecting clock asynchronous
serial I/O (Serial I/O1)
(1) Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled).
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to “0”
(Serial I/O1 disabled), the internal transmission is running (in this
case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O1 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD pin and an operation failure occurs.
(2) Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
(3) Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled).
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to “0”
(Serial I/O1 disabled), the internal transmission is running (in this
case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O1 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD pin and an operation failure occurs.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
3. Setting serial I/O1 control register again
(Serial I/O1)
Set the serial I/O1 control register again after the transmission and
the reception circuits are reset by clearing both the transmit en-
able bit and the receive enable bit to “0”.
Can be set with the
LDM instruction at
the same time
Clear both the transmit enable bit (TE) and
the receive enable bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the serial I/O1
control register
↓
Set both the transmit enable bit (TE) and the
receive enable bit (RE), or one of them to “1”
Fig 68.
Sequence of setting serial I/O1 control register
again
4. Data transmission control with referring to
transmit shift register completion flag
(Serial I/O1)
The transmit shift register completion flag changes from “1” to “0”
with a delay of 0.5 to 1.5 shift clocks. When data transmission is
controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
5. Transmit interrupt request when transmit
enable bit is set (SerialI/O1)
When the transmit interrupt is used, set the transmit interrupt en-
able bit to transmit enabled as shown in the following sequence.
(1) Set the interrupt enable bit to “0” (disabled) with CLB instruc-
tion.
(2) Prepare serial I/O for transmission/reception.
(3) Set the interrupt request bit to “0” with CLB instruction after 1
or more instruction has been executed.
(4) Set the interrupt enable bit to “1” (enabled).
<Reason>
When the transmission enable bit is set to “1”, the transmit buffer
empty flag and transmit shift register completion flag are set to “1”.
The interrupt request is generated and the transmission interrupt
request bit is set regardless of which of the two timings listed be-
low is selected as the timing for the transmission interrupt to be
generated.
Transmit buffer empty flag is set to “1”
Transmit shift register completion flag is set to “1”
6. Transmission control when external clock
is selected (Serial I/O1 clock synchronous
mode)
When an external clock is used as the synchronous clock for data
transmission, set the transmit enable bit to “1” at “H” of the SCLK1
input level. Also, write the transmit data to the transmit buffer reg-
ister (serial I/O shift register) at “H” of the SCLK1 input level.
7. Transmit data writing (Serial I/O2)
In the clock synchronous serial I/O, when selecting an external
clock as synchronous clock, write the transmit data to the serial I/
O2 register (serial I/O shift register) at “H” of the transfer clock in-
put level.
Notes on PWM
The PWM starts after the PWM enable bit is set to enable and “L”
level is output from the PWM pin.
The length of this “L” level output is as follows:
n + 1
2 f(XIN)
(s)
(Count source selection bit = “0”,
where n is the value set in the prescaler)
n + 1
f(XIN)
(s)
(Count source selection bit = “1”,
where n is the value set in the prescaler)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M38749EFT | 8-BIT, OTPROM, 6.4 MHz, MICROCONTROLLER, PQFP80 |
| M38747M4T | 8-BIT, MROM, 6.4 MHz, MICROCONTROLLER, PQFP80 |
| M38747M6T | 8-BIT, MROM, 6.4 MHz, MICROCONTROLLER, PQFP80 |
| M38747M8T | 8-BIT, MROM, 6.4 MHz, MICROCONTROLLER, PQFP80 |
| M38747MCF | 8-BIT, MROM, 6.4 MHz, MICROCONTROLLER, PQFP80 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M38588GCFP#U0 | 功能描述:IC 740/3858 MCU QZ-ROM 42SSOP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 標(biāo)準(zhǔn)包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI，I²C，UART/USART 外圍設(shè)備:POR，PWM，WDT 輸入/輸出數(shù):40 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC（J 形引線） 包裝:帶卷 (TR) |
| M38588GCSP#U0 | 功能描述:IC 740/3858 MCU QZ-ROM 42DIP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 標(biāo)準(zhǔn)包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI，I²C，UART/USART 外圍設(shè)備:POR，PWM，WDT 輸入/輸出數(shù):40 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC（J 形引線） 包裝:帶卷 (TR) |
| M3860 | 功能描述:電纜固定件和配件 FLEX LTSCG 500 RoHS:否 制造商:Heyco 類型:Cable Grips, Liquid Tight 材料:Nylon 顏色:Black 安裝方法:Cable 最大光束直徑:11.4 mm 抗拉強(qiáng)度: |
| M3860 BK001 | 制造商:Alpha Wire Company 功能描述:CBL 30COND 14AWG BLK 1000' |
| M3860 BK002 | 制造商:Alpha Wire Company 功能描述:CBL 30COND 14AWG BLK 500' |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。