參數(shù)資料
型號(hào)： M38507M8-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 41/99頁(yè)
文件大小： 1384K
代理商： M38507M8-XXXFP
41
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
A-D CONVERTER
[A-D Conversion Registers (ADL, ADH)]
0035
16
, 0036
16
The A-D conversion registers are read-only registers that store the
result of an A-D conversion. Do not read these registers during an
A-D conversion.
[A-D Control Register (ADCON)] 0034
16
The AD control register controls the A-D conversion process. Bits
0 to 2 select a specific analog input pin. Bit 4 indicates the
completion of an A-D conversion. The value of this bit remains at
“
0
”
during an A-D conversion and changes to
“
1
”
when an A-D
conversion ends. Writing
“
0
”
to this bit starts the A-D conversion.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AV
SS
and V
REF
into 1024 and outputs the divided voltages.
Channel Selector
The channel selector selects one of ports P3
0
/AN
0
to P3
4
/AN
4
and
inputs the voltage to the comparator.
Comparator and Control Circuit
The comparator and control circuit compare an analog input volt-
age with the comparison voltage, and the result is stored in the
A-D conversion registers. When an A-D conversion is completed,
the control circuit sets the A-D conversion completion bit and the
A-D interrupt request bit to
“
1
”
.
Note that because the comparator consists of a capacitor cou-
pling, set f(X
IN
) to 500 kHz or more during an A-D conversion.
When the A-D converter is operated at low-speed mode, f(X
IN
)
and f(X
CIN
) do not have the lower limit of frequency, because of
the A-D converter has a built-in self-oscillation circuit.
Fig. 39 Structure of A-D control register (spec. H)
Fig. 40 Structure of A-D conversion registers (spec. H)
Fig. 41 Block diagram of A-D converter (spec. H)
A
(
-
A
D
D
C
c
o
O
n
N
t
r
o
:
l
a
r
d
e
g
d
i
e
s
t
s
e
s
r
r
0
0
3
4
1
6
)
Analog input pin selection bits
b
b
1
b
0
0 0 0: P3
0
/AN
0
0 0 1: P3
1
/AN
1
0 1 0: P3
2
/AN
2
0 1 1: P3
3
/AN
3
1 0 0: P3
4
/AN
4
Not used (returns
“
0
”
when read)
A-D conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns
“
0
”
when read)
b7
b
0
2
1
0
-
R
b
i
t
a
r
d
e
a
a
d
d
i
d
n
g
r
e
(
e
s
s
0
0
3
6
1
b
6
b
e
f
o
r
e
0
0
3
5
1
6
)
(
A
d
d
r
e
s
s
0
0
3
6
1
6
)
(
A
d
d
r
e
s
s
0
0
3
5
1
6
)
8
-
b
i
t
r
e
a
d
i
n
g
(
R
e
a
d
o
n
b
l
y
a
d
d
r
e
s
s
0
0
3
5
1
6
)
(
A
d
d
r
e
s
s
0
0
3
5
1
6
)
b
0
8
7 b
6 b
5 b
4 b
3 b
2 b
1 b
0
7
b
0
b
9
b7
b
N
o
t
e
:
T
a
h
t
e
r
h
a
i
d
g
h
n
-
g
o
.
r
d
e
r
6
b
i
t
s
o
f
a
d
d
r
e
s
s
0
0
3
6
1
6
b
e
c
o
m
e
“
0
”
e
i
b9 b8 b7 b6 b5 b4 b3 b2
7
b0
C
h
a
n
n
e
s
e
l
e
t
o
A-D control circuit
A
-
D
c
o
n
v
e
r
s
i
o
n
l
o
w
-
o
r
d
e
r
r
e
g
i
s
t
e
r
Resistor ladder
V
REF
AV
SS
C
o
m
p
a
r
a
t
o
r
A
-
D
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
7
b
0
3
10
P
P
P
P
P
3
0
/
3
1
/
3
2
/
3
3
/
3
4
/
A
A
A
A
A
N
0
N
1
N
2
N
3
N
4
D
a
t
a
b
u
s
A
-
D
c
d
o
r
n
e
t
r
s
o
l
r
0
e
3
g
4
1
i
s
t
6
)
e
r
A
-
D
c
o
n
v
e
r
s
i
o
n
h
i
g
h
-
o
r
d
e
r
r
e
g
i
s
t
e
r
(A
d
s
0
(Address 0036
16
)
(Address 0035
16
)
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