
3850 Group (Spec. H) User’s Manual
APPLICATION
2-73
2.4 Serial I/O
(5)
Data transmission control with referring to transmit shift register completion flag (Serial I/O1)
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(6)
Transmission control when external clock is selected (Serial I/O1)
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the SCLK1 input level. Also, write the transmit data to the transmit buffer
register at “H” of the SCLK1 input level.
(7)
Transmit interrupt request when transmit enable bit is set (Serial I/O1)
When the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as shown
in the following sequence.
Set the interrupt enable bit to “0” (disabled) with CLB instruction.
Prepare serial I/O for transmission/reception.
Set the interrupt request bit to “0” with CLB instruction after 1 or more instruction has been
executed.
Set the interrupt enable bit to “1” (enabled).
q Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register completion flag are set to “1”. The interrupt request is generated and the transmission
interrupt bit is set regardless of which of the two timings listed below is selected as the timing for
the transmission interrupt to be generated.
Transmit buffer empty flag is set to “1”
Transmit shift register completion flag is set to “1”
(8)
Transmit data writing (Serial I/O2)
In the clock synchronous serial I/O, when selecting an external clock as synchronous clock, write the
transmit data to the serial I/O2 register (serial I/O shift register) at “H” of the transfer clock input level.