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參數(shù)資料
| 型號： | M38507F8FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO42 |
| 封裝： | 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42 |
| 文件頁數(shù)： | 252/287頁 |
| 文件大小： | 2969K |
| 代理商： | M38507F8FP |
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HARDWARE
3850 Group (Spec. H) User’s Manual
FUNCTIONAL DESCRIPTION
1-49
Bus Operation Modes
Read
_____
The Read mode is entered by pulling the OE pin low when the CE
_____
pin is low and the WE and RP pins are high. There are two read
modes: array, and status register, which are selected by software
command input. In read mode, the data corresponding to each soft-
ware command entered is output from the data I/O pins D0–D7. The
read array mode is automatically selected when the device is pow-
ered on or after it exits deep power down mode.
Output Disable
_____
The output disable mode is entered by pulling the CE pin low and the
_____
WE, OE, and RP pins high. Also, the data I/O pins are placed in the
high-impedance state.
Standby
_____
The standby mode is entered by driving the CE pin high when the RP
pin is high. Also, the data I/O pins are placed in the high-impedance
_____
state. However, if the CE pin is set high during erase or program
operation, the internal control circuit does not halt immediately and
normal power consumption is required until the operation under way
is completed.
Write
_____
The write mode is entered by pulling the WE pin low when the CE pin
_____
is low and the OE and RP pins are high. In this mode, the device
accepts the software commands or write data entered from the data
I/O pins. A program, erase, or some other operation is initiated de-
pending on the content of the software command entered here. The
input data such as address and software command is latched at the
_____
rising edge of WE or CE whichever occurs earlier.
Deep Power Down
_____
The deep power down is entered by pulling the RP pin low. Also, the
data I/O pins are placed in the high-impedance state. When the de-
vice is freed from deep power down mode, the read array mode is
selected and the content of the status register is set to “8016”. If the
_____
RP pin is pulled low during erase or program operation, the opera-
tion under way is canceled and the data in the relevant block be-
comes invalid.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in
Figure 44 can be rewritten. The BSEL pin is used to choose between
these two areas. The user ROM area is selected by pulling the BSEL
input low; the boot ROM area is selected by driving the BSEL input high.
Both areas of flash memory can be operated on in the same way.
Program and block erase operations can be performed in the user
ROM area. The user ROM area and its block is shown in Figure 44.
The user ROM area is 32 Kbytes in size. In parallel I/O mode, it is
located at addresses 800016 through FFFF16. The boot ROM area is
4 Kbytes in size. In parallel I/O mode, it is located at addresses
F00016 through FFFF16. Make sure program and block erase opera-
tions are always performed within this address range. (Access to
any location outside this address range is prohibited.)
In the Boot ROM area, an erase block operation is applied to only
one 4 Kbyte block. The boot ROM area has had a standard serial
I/O mode control program stored in it when shipped from the
Renesas factory. Therefore, using the device in standard serial in-
put/output mode, you do not need to write to the boot ROM area.
Functional Outline (Parallel I/O Mode)
In parallel I/O mode, bus operation modes—Read, Output Disable,
Standby, Write, and Deep Power Down—are selected by the status
_____
of the CE, OE, WE, and RP input pins.
The contents of erase, program, and other operations are selected
by writing a software command. The data, status register, etc. in
memory can only be read out by a read after software command
input.
Program and erase operations are controlled using software com-
mands.
The following explains about bus operation modes, software com-
mands, and status register.
D0 to D7
Data output
Status register data output
High impedance
Command/data input
Command input
High impedance
_____
RP
VIH
VIL
______
WE
VIH
X
VIL
X
_____
OE
VIL
VIH
X
VIH
X
_____
CE
VIL
VIH
VIL
X
Pin name
Mode
Array
Status register
Output disabled
Stand by
Program
Write
Erase all blocks
Block erase
Deep power down
Read
Note : X can be VIL or VIH.
Table 12 Relationship between control signals and bus operation modes
Parallel I/O Mode
The parallel I/O mode is entered by making connections shown in
Figure 52 and then turning the Vcc power supply on.
Address
The user ROM is only one block as shown in Figure 44. The block
address referred to in this data sheet is the maximum address value
of each block.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| M38507F8FP#U1 | 制造商:Renesas Electronics Corporation 功能描述:MCU 8BIT 740 CISC 32KB FLASH 5V 42SSOP - Trays |
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| M38507F8FP(#U1) | 制造商:Renesas Electronics Corporation 功能描述: |
| M3851 BK001 | 制造商:Alpha Wire Company 功能描述:CBL 7COND 14AWG BLK 1000' |
| M3851 BK002 | 制造商:Alpha Wire Company 功能描述:CBL 7COND 14AWG BLK 500' |
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