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參數(shù)資料
| 型號(hào)： | M38049FFLHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁(yè)數(shù)： | 90/129頁(yè) |
| 文件大?。?/td> | 1721K |
| 代理商： | M38049FFLHP |
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Rev.1.00
Oct 27, 2008
Page 63 of 128
REJ03B0266-0100
3804 Group (Spec.L)
MULTI-MASTER I2C-BUS INTERFACE
The 3804 group (Spec. L) has the multi-master I2C-BUS
interface. The multi-master I2C-BUS interface is a serial
communications circuit, conforming to the Philips I2C-BUS data
transfer format. This interface, offering both arbitration lost
detection and a synchronous functions, is useful for the multi-
master serial communications.
functions.
This multi-master I2C-BUS interface consists of the I2C slave
address registers 0 to 2, the I2C data shift register, the I2C clock
control register, the I2C control register, the I2C status register,
the I2C START/STOP condition control register, the I2C special
mode control register, the I2C special mode status register, and
other control circuits.
When using the multi-master I2C-BUS interface, set 1 MHz or
more to the internal clock
φ.
System clock
φ = f(XIN)/2 (high-speed mode)
φ = f(XIN)/8 (middle-speed mode)
NOTE:
1. We are not responsible for any third party’s infringement of
patent rights or other rights attributable to the use of the
control function (bit 6 of the I2C control register at address
002E16) for connections between the I2C-BUS interface and
ports (SCL1, SCL2, SDA1, and SDA2).
Fig. 60 Block diagram of multi-master I2C-BUS interface
*: Purchase of Renesas Technology Corporation’s I2C components conveys a license under the Philips I2C Patent Rights
to use these components an I2C system, provided that the system conforms to the I2C Standard Specification as defined
by Philips.
Table 9
Multi-master I2C-BUS interface functions
Item
Function
Format
In conformity with Philips I2C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
Communication
mode
In conformity with Philips I2C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
SCL clock
frequency
16.1 kHz to 400 kHz (at
φ = 4 MHz)
I2C slave address registers 0 to 2
b7
b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Serial data
(SDA)
Address comparator
b7
I2C data shift register
b0
Interrupt
generating
circuit
System clock
(
φ)
b7
MST TRX BB
PIN
AL AAS AD0 LRB
b0
S1
Noise
elimination
circuit
Data
control
circuit
AL
circuit
BB
circuit
Clock
control
circuit
Noise
elimination
circuit
b7
b0
ACK
BIT
FAST
MODE CCR4 CCR3 CCR2 CCR1 CCR0
Clock division
S0
S2
S0D0-2
SIS
SIP SSC4 SSC3 SSC2 SSC1 SSC0
b7
b0
TISS
TSEL
10BIT
SAD
ALS
BC2
BC1 BC0
S1D
Bit counter
ES0
I2C clock control register
I2C status register
Internal data bus
Interrupt
generating
circuit
Interrupt request signal
(SCL, SDA, IRQ)
Interrupt request signal
(I2CIRQ)
b7
b0
SPCF
S3
PIN2
AAS2 AAS1 AAS0
b7
b0
SPCFL
S3D
PIN2
HD
PIN2
IN
HSLAD ACKI
CON
I 2C special mode control register
I 2C special mode status register
Serial clock
(SCL)
S2D I2C START/STOP condition control
register
I2C control register
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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