參數(shù)資料
型號: M38049FFLHP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 103/129頁
文件大?。?/td> 1721K
代理商: M38049FFLHP
Rev.1.00
Oct 27, 2008
Page 75 of 128
REJ03B0266-0100
3804 Group (Spec.L)
Example of Master Transmission
An example of master transmission in the standard clock mode,
at the SCL frequency of 100 kHz and in the ACK return mode is
shown below.
(1) Set a slave address in the high-order 7 bits of the I2C slave
address register and “0” into the RWB bit.
(2) Set the ACK return mode and SCL = 100 kHz by setting
“8516” in the I2C clock control register (S2: address 001516).
(3) Set “0016” in the I2C status register (S1: address 001316) so
that transmission/reception mode can become initializing
condition.
(4) Set a communication enable status by setting “0816” in the
I2C control register (S1D: address 001416).
(5) Confirm the bus free condition by the BB flag of the I2C
status register (S1: address 001316).
(6) Set the address data of the destination of transmission in the
high-order 7 bits of the I2C data shift register (S0: address
001116) and set “0” in the least significant bit.
(7) Set “F016” in the I2C status register (S1: address 001316) to
generate a START condition. At this time, an SCL for 1
byte and an ACK clock automatically occur.
(8) Set transmit data in the I2C data shift register (S0: address
00 1116 ). At th is t i m e , an SCL and an ACK clock
automatically occur.
(9) When transmitting control data of more than 1 byte, repeat
step (8).
(10) Set “D016” in the I2C status register (S1: address 001316) to
generate a STOP condition if ACK is not returned from
slave reception side or transmission ends.
Example of Slave Reception
An example of slave reception in the high-speed clock mode, at
the SCL frequency of 400 kHz, in the ACK non-return mode and
using the addressing format is shown below.
(1) Set a slave address in the high-order 7 bits of the I2C slave
address register and “0” in the RWB bit.
(2) Set the no ACK clock mode and SCL = 400 kHz by setting
“2516” in the I2C clock control register (S2: address 001516).
(3) Set “0016” in the I2C status register (S1: address 001316) so
that transmission/reception mode can become initializing
condition.
(4) Set a communication enable status by setting “0816” in the
I2C control register (S1D: address 001416).
(5) When a START condition is received, an address
comparison is performed.
(6) When all transmitted addresses are “0” (general call):
AD0 of the I2C status register (S1: address 001316) is set to
“1” and an interrupt request signal occurs.
When the transmitted addresses agree with the address set
in (1):
AAS of the I2C status register (S1: address 001316) is set to
“1” and an interrupt request signal occurs.
In the cases other than the above AD0 and AAS of the I2C
status register (S1: address 001316) are set to “0” and no
interrupt request signal occurs.
(7) Set dummy data in the I2C data shift register (S0: address
001116).
(8) When receiving control data of more than 1 byte, repeat step
(7).
(9) When a STOP condition is detected, the communication
ends.
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