參數(shù)資料
型號: M38049FFLHP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 102/129頁
文件大?。?/td> 1721K
代理商: M38049FFLHP
Rev.1.00
Oct 27, 2008
Page 74 of 128
REJ03B0266-0100
3804 Group (Spec.L)
Address Data Communication
There are two address data communication formats, namely, 7-
bit addressing format and 10-bit addressing format. The
respective address communication formats are described below.
7-bit addressing format
To adapt the 7-bit addressing format, set the 10BIT SAD bit of
the I2C control register (S1D: address 001416) to “0”. The first 7-
bit address data transmitted from the master is compared with the
high-order 7-bit slave address stored in the I2C slave address
register. At the time of this comparison, address comparison of
the RWB bit of the I2C slave address register is not performed.
For the data transmission format when the 7-bit addressing
format is selected, refer to Figure 73, (1) and (2).
10-bit addressing format
To adapt the 10-bit addressing format, set the 10BIT SAD bit of
the I2C control register (S1D: address 001416) to “1”. An address
comparison is performed between the first-byte address data
transmitted from the master and the 8-bit slave address stored in
the I2C slave address register. At the time of this comparison, an
address comparison between the RWB bit of the I2C slave
address register and the R/W bit which is the last bit of the
address data transmitted from the master is made. In the 10-bit
addressing mode, the RWB bit which is the last bit of the address
data not only specifies the direction of communication for
control data, but also is processed as an address data bit.
When the first-byte address data agree with the slave address, the
AAS bit of the I2C status register (S1: address 001316) is set to
“1”. After the second-byte address data is stored into the I2C data
shift register (S0: address 001116), perform an address
comparison between the second-byte data and the slave address
by software. When the address data of the 2 bytes agree with the
slave address, set the RWB bit of the I2C slave address register to
“1” by software. This processing can make the 7-bit slave
address and R/W data agree, which are received after a
RESTART condition is detected, with the value of the I2C slave
address register. For the data transmission format when the 10-
bit addressing format is selected, refer to Figure 73, (3) and (4)
.
Fig. 73 Address data communication format
7 bits
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
“0”
(2) A master-receiver receives data from a slave-transmitter
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
“1”
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
1 to 8 bits
7 bits
1 to 8 bits
8 bits
7 bits
1 to 8 bits
: Master to slave
: Slave to master
S: START condition
P: STOP condition
A: ACK bit
R/W: Read/Write bit
Sr: Restart condition
“1”
“0”
S
Slave address R/W
Data
A/A
Data
AA
P
S
Slave address R/W
Data
A
Data
AA
P
S
R/W
Slave address
1st 7 bits
Data
A/A
Data
AA
P
A
R/W
Data
A
Data
AA
P
S
R/W
A
Sr
Slave address
1st 7 bits
Slave address
2nd bytes
Slave address
2nd bytes
Slave address
1st 7 bits
相關(guān)PDF資料
PDF描述
M38049FFLSP 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PDIP64
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