參數(shù)資料
型號： M38039FFLHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 94/121頁
文件大?。?/td> 2071K
代理商： M38039FFLHP
Rev.1.01
Jan 25, 2008
Page 72 of 117
REJ03B0212-0101
3803 Group (Spec.L)
Fig 70. Structure of flash memory control register 2
Figure 71 shows a flowchart for setting/releasing CPU rewrite mode.
Fig 71. CPU rewrite mode set/release flowchart be sure to execute
Flash memory control register 2
(FMCR2: address : 0FE216: initial value: 4516)
Not used
Not used (do not write “1” to this bit.)
Not used
All user block E/W enable bit(1, 2)
0 : E/W disabled
1 : E/W enabled
Not used
b7
b0
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession. For this bit to be set to “0”, write “0” only to this
bit.
2: Effective only when the CPU rewrite mode select bit = “1”.
Table 11 State of E/W inhibition function
All user block E/W
enable bit
8 KB user block
E/W enable bit
8 KB
× 2 block
Addresses C00016 to FFFF16
16 KB + 24 KB block
Addresses 200016 to BFFF16
Data block
Addresses 100016 to 1FFF16
0
E/W disabled
E/W enabled
0
1
E/W disabled
E/W enabled
1
0
E/W disabled
E/W enabled
1
E/W enabled
Start
Single-chip mode or Boot mode
Set CPU mode register(1)
Jump to control program transferred to internal RAM
(Subsequent operations are executed by control program in
this RAM)
Transfer CPU rewrite mode control program to internal RAM
Set CPU rewrite mode select bit to “1” (by writing “0” and
then “1” in succession)
Using software command executes erase, program, or other
operation
End
Write “0” to CPU rewrite mode select bit
Set all user block E/W enable bit to “1” (by writing “0” and
then “1” in succession)
Set 8 KB user block E/W enable bit (At E/W disabled; writing
“0” , at E/W enabled;
writing “0” and then “1” in succession
Execute read array command(2)
Set all user block E/W enable bit to “0”
Set 8 KB user block E/W enable bit to “0”
Notes 1: Set the main clock as follows depending on the clock division ratio selection bits of CPU mode register (bits 6, 7 of address 003B16).
2: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute the read array
command.
相關(guān)PDF資料
PDF描述
M38039FFLWG 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PBGA64
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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