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參數(shù)資料
| 型號： | M38039FFLHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 66/121頁 |
| 文件大?。?/td> | 2071K |
| 代理商： | M38039FFLHP |
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Rev.1.01
Jan 25, 2008
Page 47 of 117
REJ03B0212-0101
3803 Group (Spec.L)
<Notes concerning serial I/O1>
1. Notes when selecting clock synchronous serial I/O
1.1 Stop of transmission operation
Note
Clear the serial I/O1 enable bit and the transmit enable bit to
“0” (serial I/O and transmit disabled).
Reason
Since transmission is not stopped and the transmission circuit
is not initialized even if only the serial I/O1 enable bit is
cleared to “0” (serial I/O disabled), the internal transmission is
running (in this case, since pins TXD1, RXD1, SCLK1, and
SRDY1 function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in
this state, data starts to be shifted to the transmit shift register.
When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TXD1 pin and an
operation failure occurs.
1.2 Stop of receive operation
Note
Clear the receive enable bit to “0” (receive disabled), or clear
the serial I/O1 enable bit to “0” (serial I/O disabled).
1.3 Stop of transmit/receive operation
Note
Clear both the transmit enable bit and receive enable bit to “0”
(transmit and receive disabled).
(when dat a is transmit ted and received i n the clock
synchronous serial I/O mode, any one of data transmission and
reception cannot be stopped.)
Reason
In the clock synchronous serial I/O mode, the same clock is
used for transmission and reception. If any one of transmission
and reception is disabled, a bit error occurs because
transmission and reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also
operates for data reception. Accordingly, the transmission
circuit does not stop by clearing only the transmit enable bit to
“0” (transmit disabled). Also, the transmission circuit is not
initialized by clearing the serial I/O1 enable bit to “0” (serial
I/O disabled) (refer to 1.1).
2. Notes when selecting clock asynchronous serial I/O
2.1 Stop of transmission operation
Note
Clear the transmit enable bit to “0” (transmit disabled). The
transmission operation does not stop by clearing the serial
I/O1 enable bit to “0”.
Reason
Since transmission is not stopped and the transmission circuit
is not initialized even if only the serial I/O1 enable bit is
cleared to “0” (serial I/O disabled), the internal transmission is
running (in this case, since pins TXD1, RXD1, SCLK1, and
SRDY1 function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in
this state, data starts to be shifted to the transmit shift register.
When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TXD1 pin and an
operation failure occurs.
2.2 Stop of receive operation
Note
Clear the receive enable bit to “0” (receive disabled).
2.3 Stop of transmit/receive operation
Note 1 (only transmission operation is stopped)
Clear the transmit enable bit to “0” (transmit disabled). The
transmission operation does not stop by clearing the serial
I/O1 enable bit to “0”.
Reason
Since transmission is not stopped and the transmission circuit
is not initialized even if only the serial I/O1 enable bit is
cleared to “0” (serial I/O disabled), the internal transmission is
running (in this case, since pins TXD1, RXD1, SCLK1, and
SRDY1 function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in
this state, data starts to be shifted to the transmit shift register.
When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TXD1 pin and an
operation failure occurs.
Note 2 (only receive operation is stopped)
Clear the receive enable bit to “0” (receive disabled).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M38039FFLHP#U0 | 功能描述:IC 3803 MCU FLASH 64LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 產(chǎn)品培訓(xùn)模塊:CAN Basics Part-1 CAN Basics Part-2 Electromagnetic Noise Reduction Techniques Part 1 M16C Product Overview Part 1 M16C Product Overview Part 2 標準包裝:1 系列:M16C™ M32C/80/87 核心處理器:M32C/80 芯體尺寸:16/32-位 速度:32MHz 連通性:EBI/EMI，I²C，IEBus，IrDA，SIO，UART/USART 外圍設(shè)備:DMA，POR，PWM，WDT 輸入/輸出數(shù):121 程序存儲器容量:384KB（384K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:24K x 8 電壓 - 電源 (Vcc/Vdd):3 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 34x10b，D/A 2x8b 振蕩器型:內(nèi)部 工作溫度:-20°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤 產(chǎn)品目錄頁面:749 (CN2011-ZH PDF) 配用:R0K330879S001BE-ND - KIT DEV RSK M32C/87 |
| M38039FFLKP#U0 | 制造商:Renesas 功能描述:MCU 8-bit 740 CISC 60KB Flash 3.3V/5V 64-Pin LQFP Tray |
| M38039FFLKPU0 | 制造商:Renesas Electronics Corporation 功能描述:8bit MCU,3803,61K ProgROM,2K RAM,LQFP64 |
| M38039FFSP | 制造商:Mitsubishi Electric 功能描述:8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PDIP64 |
| M38039G4HHP#U0 | 功能描述:IC 740/3803 MCU QZROM 64LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 標準包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI，I²C，UART/USART 外圍設(shè)備:POR，PWM，WDT 輸入/輸出數(shù):40 程序存儲器容量:- 程序存儲器類型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC（J 形引線） 包裝:帶卷 (TR) |
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